diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index fd188a1..9db6a9d 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -176,7 +176,7 @@
 			reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
 }
 
-void haswell_early_initialization(int chipset_type)
+void haswell_early_initialization(void)
 {
 	/* Setup all BARs required for early PCIe and raminit */
 	haswell_setup_bars();
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bd44168..c393049 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,7 +189,7 @@
 
 void intel_northbridge_haswell_finalize_smm(void);
 
-void haswell_early_initialization(int chipset_type);
+void haswell_early_initialization(void);
 void haswell_late_initialization(void);
 void set_translation_table(int start, int end, u64 base, int inc);
 void haswell_unhide_peg(void);