src/northbridge/via: Remove commented code
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16898
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index aff62f2..4878571 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -326,9 +326,8 @@
/* Fast cycle control for CPU-to-DRAM Read Cycle 0:Disabled.
* This CPU bus controller will wait for all data */
- ////pci_mod_config8(HOST_BUS, 0x51, (1 << 7), 0);
+
/* Memory to CPU bus Controller Conversion Mode 1: Synchronous mode */
- ////pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 1));
}
static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm)
@@ -1335,7 +1334,6 @@
/* FIXME: Except that we have not yet told the MCU what
* the geometry of the DIMM is, hence we don't trust
* this test for now */
- ////continue;
}
/* Good. We should be able to use this DIMM */
/* That's it. We're done */
@@ -1614,14 +1612,8 @@
/* Tri-state MCSi# when rank is in self-refresh */
pci_mod_config8(MCU, 0x99, 0, 0x0f);
- ////pci_write_config8(MCU, 0x69, 0xe7);
/* Enable paging mode and 8 page registers */
pci_mod_config8(MCU, 0x69, 0, 0xe5);
- ////pci_write_config8(MCU, 0x72, 0x0f);
-
- ////pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */
- ////pci_write_config8(MCU, 0x98, 0xba); /* self-refresh II */
- ////pci_write_config8(MCU, 0x9a, 0x80); /* self-refresh III */
/* Enable automatic triggering of short ZQ calibration */
pci_write_config8(MCU, 0xc8, 0x80);