tree f702e193c781a82a5e8b57fa2bb80c5bb6ca9804
parent 4eadcb053795514ad6fdd61b0b9a95729dee8bd0
author Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> 1588213507 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> 1588632316 +0000

vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163

Update FSP headers for Tiger Lake platform generated based FSP
version 3163. Which includes below additional UPDs:

FSPM:
-BootFrequency
-SerialIoUartDebugMode
FSPS:
-PcieRpPmSci
-PchPmWoWlanEnable
-PchPmWoWlanDeepSxEnable
-PchPmLanWakeFromDeepSx

BUG=b:155315876
BRANCH=none
TEST=build and boot ripto/volteer

Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ida87ac7dd7f5fd7ee0459ae1037a8df816976083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40898
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>