arch/x86/ioapic: Promote ioapic_get_sci_pin()
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.
Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 0d2c517..7a64c11 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -49,8 +49,6 @@
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->sci_int = ACPI_SCI_IRQ;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 09c35db..1fbff53 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -16,6 +16,7 @@
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/lpc.h>
+#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/southbridge.h>
@@ -34,6 +35,13 @@
pm_write8(PM_SERIRQ_CONF, byte);
}
+void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
+{
+ *gsi = ACPI_SCI_IRQ;
+ *irq = ACPI_SCI_IRQ;
+ *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;
+}
+
static void fch_ioapic_init(void)
{
fch_enable_ioapic_decode();
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index 2943d7d..d97dc09 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -52,8 +52,6 @@
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->sci_int = ACPI_SCI_IRQ;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index 8fb7237..94cb246 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -51,8 +51,6 @@
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->sci_int = ACPI_SCI_IRQ;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index ea2a997..427fb74 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -52,8 +52,6 @@
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->sci_int = ACPI_SCI_IRQ;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 341d9e0..5d34f47 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -56,8 +56,6 @@
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->sci_int = ACPI_SCI_IRQ;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 39f13b6..9aef608 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -50,8 +50,6 @@
{
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
- fadt->sci_int = ACPI_SCI_IRQ;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c
index a76d161..c01a79a 100644
--- a/src/soc/intel/baytrail/fadt.c
+++ b/src/soc/intel/baytrail/fadt.c
@@ -2,7 +2,6 @@
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
-#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include "chip.h"
@@ -11,8 +10,6 @@
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = acpi_sci_int();
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c
index a76d161..d071b92 100644
--- a/src/soc/intel/braswell/fadt.c
+++ b/src/soc/intel/braswell/fadt.c
@@ -11,8 +11,6 @@
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = acpi_sci_int();
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c
index 9355670..2ffebc3 100644
--- a/src/soc/intel/broadwell/pch/fadt.c
+++ b/src/soc/intel/broadwell/pch/fadt.c
@@ -10,8 +10,6 @@
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = 9;
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 1ddee34..9aaca21 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -36,6 +36,15 @@
register_new_ioapic_gsi0(VIO_APIC_VADDR);
}
+#define ACPI_SCI_IRQ 9
+
+void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
+{
+ *gsi = ACPI_SCI_IRQ;
+ *irq = ACPI_SCI_IRQ;
+ *flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+}
+
static void enable_hpet(struct device *dev)
{
size_t i;
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 50854fa..1b5538f 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -94,8 +94,6 @@
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = acpi_sci_int();
-
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
diff --git a/src/soc/intel/quark/lpc.c b/src/soc/intel/quark/lpc.c
index 92b7249..115a7b9 100644
--- a/src/soc/intel/quark/lpc.c
+++ b/src/soc/intel/quark/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/iomap.h>
@@ -34,6 +35,13 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
+/* Implemented just to fill FADT SCI_INT as 0. */
+void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
+{
+ *irq = 0;
+ *gsi = 0;
+}
+
static struct device_operations device_ops = {
.read_resources = pmc_read_resources,
.set_resources = pci_dev_set_resources,