commit e6ff1596e7417d24746162b3a567bcb6dd9ef988
author Martin Roth <martinroth@google.com> Sat Jun 24 21:34:29 2017 -0600
committer Martin Roth <martinroth@google.com> Thu Jul 13 23:54:32 2017 +0000
tree 36db0c03c6122c9b31d0f25c40a2f5745371a179
parent fed4303b45aa3c8ba98cd2ab90cf5bf023fc6aae

soc/intel: add IS_ENABLED() around Kconfig symbol references

Change-Id: I3c5f9e0d3d1efdd83442ce724043729c8648ea64
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/broadwell/romstage/raminit.c

diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 10cb733..34ab39c 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -22,7 +22,7 @@
 #include <device/pci_def.h>
 #include <lib.h>
 #include <string.h>
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #endif
@@ -65,7 +65,7 @@
 		reset_system();
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
 		if (pei_data->boot_mode == ACPI_S0) {
 			/* Ensure EC is running RO firmware. */
 			google_chromeec_check_ec_image(EC_IMAGE_RO);
@@ -110,7 +110,7 @@
 	if (pei_data->boot_mode != ACPI_S3) {
 		cbmem_initialize_empty();
 	} else if (cbmem_initialize()) {
-#if CONFIG_HAVE_ACPI_RESUME
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
 		/* Failed S3 resume, reset to come up cleanly */
 		reset_system();