diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
new file mode 100644
index 0000000..4e3833e
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/devicetree.cb
@@ -0,0 +1,80 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip soc/intel/fsp_baytrail
+
+	#### ACPI Register Settings ####
+	register "fadt_pm_profile" = "PM_UNSPECIFIED"
+	register "fadt_boot_arch"  = "ACPI_FADT_LEGACY_FREE"
+
+	#### FSP register settings ####
+	register "SataMode"             = "SATA_MODE_AHCI"
+	register "MrcInitSPDAddr1"      = "SPD_ADDR_DEFAULT"
+	register "MrcInitSPDAddr2"      = "SPD_ADDR_DEFAULT"
+	register "MrcInitTsegSize"      = "TSEG_SIZE_DEFAULT"
+	register "MrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
+	register "eMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
+	register "IgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
+	register "ApertureSize"         = "APERTURE_SIZE_DEFAULT"
+	register "GttSize"              = "GTT_SIZE_DEFAULT"
+	register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
+	register "AzaliaAutoEnable"     = "AZALIA_FOLLOWS_DEVICETREE"
+	register "LpeAcpiModeEnable"    = "LPE_ACPI_MODE_DISABLED"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end	# 8086 0F00 - SoC router		-
+		device pci 02.0 on end	# 8086 0F31 - GFX				micro HDMI
+		device pci 03.0 off end # 8086 0F38 - MIPI				-
+
+		device pci 10.0 off end	# 8086 0F14 - EMMC Port			-
+		device pci 11.0 off end	# 8086 0F15 - SDIO Port			-
+		device pci 12.0 on end	# 8086 0F16 - SD Port			MicroSD on SD3
+		device pci 13.0 on end	# 8086 0F23 - SATA AHCI			Onboard & HSEC
+		device pci 14.0 on end	# 8086 0F35 - USB XHCI			Onboard & HSEC
+		device pci 15.0 on end	# 8086 0F28 - LP Engine Audio	LSEC
+		device pci 17.0 off end	# 8086 0F50 - MMC Port			-
+		device pci 18.0 on end	# 8086 0F40 - SIO - DMA			-
+		device pci 18.1 off end	# 8086 0F41 -   I2C Port 1 (0)	-
+		device pci 18.2 off end	# 8086 0F42 -   I2C Port 2 (1)	- (testpoints)
+		device pci 18.3 off end	# 8086 0F43 -   I2C Port 3 (2)	-
+		device pci 18.4 off end	# 8086 0F44 -   I2C Port 4 (3)	-
+		device pci 18.5 off end	# 8086 0F45 -   I2C Port 5 (4)	-
+		device pci 18.6 on end	# 8086 0F46 -   I2C Port 6 (5)	LSEC
+		device pci 18.7 on end	# 8086 0F47 -   I2C Port 7 (6)	HSEC
+		device pci 1a.0 on end	# 8086 0F18 - TXE				-
+		device pci 1b.0 off end	# 8086 0F04 - HD Audio			-
+		device pci 1c.0 off end	# 8086 0F48 - PCIe Port 1 (0)	-
+		device pci 1c.1 off end	# 8086 0F4A - PCIe Port 2 (1)	-
+		device pci 1c.2 on end	# 8086 0F4C - PCIe Port 3 (2)	Onboard GBE
+		device pci 1c.3 on end	# 8086 0F4E - PCIe Port 4 (3)	HSEC
+		device pci 1d.0 off end	# 8086 0F34 - USB EHCI			-
+		device pci 1e.0 on end	# 8086 0F06 - SIO - DMA			-
+		device pci 1e.1 on end	# 8086 0F08 -   PWM 1			LSEC
+		device pci 1e.2 on end	# 8086 0F09 -   PWM 2			LSEC
+		device pci 1e.3 on end	# 8086 0F0A -   HSUART 1		LSEC
+		device pci 1e.4 on end	# 8086 0F0C -   HSUART 2		LSEC
+		device pci 1e.5 on end	# 8086 0F0E -   SPI				LSEC
+		device pci 1f.0 on end	# 8086 0F1C - LPC bridge		No connector
+		device pci 1f.3 on end	# 8086 0F12 - SMBus 0			SPC
+	end
+end