| commit | e69461dc25193bc792ba50b7d48081bdccd6e066 | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Wed May 05 14:45:28 2021 +0200 |
| committer | Arthur Heymans <arthur@aheymans.xyz> | Wed Apr 27 13:04:12 2022 +0000 |
| tree | c7c3c611a29b740fbfb0635110aa163547993ebe | |
| parent | 6afd3c1ceaba3a99ae4add821934ce6d04faa95d [diff] |
nb/intel/pineview: Use cbfs mcache There is plenty of cache available to increase DCACHE_RAM_SIZE to allow the use of cbfs mcache. Tested on Gigabyte GA-D510UD, still boots and resumes. Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 681ca41..ed661b6 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -17,7 +17,7 @@ config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 config DCACHE_BSP_STACK_SIZE hex
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index b2a0730..92185f5 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig
@@ -13,7 +13,6 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_GMA_ACPI - select NO_CBFS_MCACHE config VGA_BIOS_ID string