commit e6063fee5c954d5acd80fd51e11aeac31e83d13d
author Stefan Reinauer <reinauer@chromium.org> Mon Apr 30 14:57:51 2012 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Tue May 01 19:27:34 2012 +0200
tree 331b26df9de6e8b4e08473432de1d293602487df
parent a1155b47ca42ad1813c36e1d6de6e8116ae13845

Fix Sandybridge/Ivybridge mainboards according to code review

This fixes a few cosmetics with the following three boards:

 - Intel Emerald Lake 2
 - Samsung ChromeBook
 - Samsung ChromeBox

The following issues were fixed:

 - rely on include path in ASL code instead of specifying relative
   paths
 - use updated ALIGN_CURRENT in acpi_tables.c
 - use preprocessor defines instead of hard coded values where possible

Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)

src/mainboard/intel/emeraldlake2/romstage.c

diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 23d1d6b..0cf113b 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -188,17 +188,17 @@
 #endif
 	struct pei_data pei_data = {
 		pei_version: PEI_VERSION,
-		mchbar: 0xfed10000,
-		dmibar: 0xfed18000,
-		epbar: 0xfed19000,
-		pciexbar: 0xf0000000,
-		smbusbar: 0x400,
+		mchbar: DEFAULT_MCHBAR,
+		dmibar: DEFAULT_DMIBAR,
+		epbar: DEFAULT_EPBAR,
+		pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+		smbusbar: SMBUS_IO_BASE,
 		wdbbar: 0x4000000,
 		wdbsize: 0x1000,
-		hpet_address: 0xfed00000,
-		rcba: 0xfed1c000,
-		pmbase: 0x500,
-		gpiobase: 0x480,
+		hpet_address: HPET_ADDR,
+		rcba: DEFAULT_RCBABASE,
+		pmbase: DEFAULT_PMBASE,
+		gpiobase: DEFAULT_GPIOBASE,
 		thermalbase: 0xfed08000,
 		system_type: 0, // 0 Mobile, 1 Desktop/Server
 		tseg_size: CONFIG_SMM_TSEG_SIZE,