commit e6063fee5c954d5acd80fd51e11aeac31e83d13d
author Stefan Reinauer <reinauer@chromium.org> Mon Apr 30 14:57:51 2012 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Tue May 01 19:27:34 2012 +0200
tree 331b26df9de6e8b4e08473432de1d293602487df
parent a1155b47ca42ad1813c36e1d6de6e8116ae13845

Fix Sandybridge/Ivybridge mainboards according to code review

This fixes a few cosmetics with the following three boards:

 - Intel Emerald Lake 2
 - Samsung ChromeBook
 - Samsung ChromeBox

The following issues were fixed:

 - rely on include path in ASL code instead of specifying relative
   paths
 - use updated ALIGN_CURRENT in acpi_tables.c
 - use preprocessor defines instead of hard coded values where possible

Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)

src/mainboard/intel/emeraldlake2/acpi/superio.asl

diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl
index f803aaf..a50c4b3 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl
@@ -32,4 +32,4 @@
 #define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
 #define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
 
-#include "../../../../superio/smsc/sio1007/acpi/superio.asl"
+#include "superio/smsc/sio1007/acpi/superio.asl"