tree 4a2ce829c27efc766a068d6cd85d63d487799a9e
parent 88019ddbdf367ce8e44fd46d46ad042f9ca78355
author Sridhar Siricilla <sridhar.siricilla@intel.com> 1651168921 +0530
committer Felix Held <felix-coreboot@felixheld.de> 1669039464 +0000

soc/intel/common: Add support to read CPU and PCH Trace Hub modes

The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.

For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>