| commit | e5ac30060298626cf12972209ea81a77d0569cde | [log] [tgz] |
|---|---|---|
| author | Jeff Daly <jeffd@silicom-usa.com> | Mon Jan 10 23:47:35 2022 -0500 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Fri Jun 17 14:52:41 2022 +0000 |
| tree | eb34efb014f6f3afe6cefbcd831c060c5ce4a82f | |
| parent | 24f7554e070ce11d902b7b78846158f802c4b952 [diff] [blame] |
soc/intel/denverton_ns: enable Denverton to use common SoC SPI code Use Intel common SoC SPI code for Denverton refactor Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 256e01a..3460718 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c
@@ -197,6 +197,7 @@ PCI_DID_INTEL_ADP_M_N_SPI1, PCI_DID_INTEL_ADP_M_SPI2, PCI_DID_INTEL_SPR_HWSEQ_SPI, + PCI_DID_INTEL_DNV_SPI, 0 };