soc/intel/denverton_ns: enable Denverton to use common SoC SPI code
Use Intel common SoC SPI code for Denverton refactor
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
index 256e01a..3460718 100644
--- a/src/soc/intel/common/block/spi/spi.c
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -197,6 +197,7 @@
PCI_DID_INTEL_ADP_M_N_SPI1,
PCI_DID_INTEL_ADP_M_SPI2,
PCI_DID_INTEL_SPR_HWSEQ_SPI,
+ PCI_DID_INTEL_DNV_SPI,
0
};
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index a1cd788..8544ac5 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -34,6 +34,7 @@
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR
diff --git a/src/soc/intel/denverton_ns/spi.c b/src/soc/intel/denverton_ns/spi.c
index 087fdab..27ad5ae 100644
--- a/src/soc/intel/denverton_ns/spi.c
+++ b/src/soc/intel/denverton_ns/spi.c
@@ -1,10 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <intelblocks/fast_spi.h>
-#include <spi-generic.h>
+#include <intelblocks/spi.h>
+#include <soc/pci_devs.h>
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
- { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
-};
+int spi_soc_devfn_to_bus(unsigned int devfn)
+{
+ /* Denverton doesn't have GSPI controllers, only Fast SPI */
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
+ if (devfn == PCH_DEVFN_SPI)
+ return 0;
+ else
+ return -1;
+}