commit e4eba133cc73761fb7ca4bb5de8b8a01633b2be1
author Arthur Heymans <arthur@aheymans.xyz> Thu Jul 13 14:02:42 2023 +0200
committer Felix Held <felix-coreboot@felixheld.de> Thu Sep 28 16:28:59 2023 +0000
tree 6e738e907414195781d8840f54ca3b81ed9941fe
parent 8f1c70706056723f2be33ef15b1bc06092f1160f

soc/amd/genoa: Deal with memory map for 32M or larger flash

Only the lower half of the flash gets memory mapped below 4G in the
current setup.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76499
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/genoa/Kconfig

diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 705805e..7ef5707 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -15,6 +15,7 @@
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
 	select UNKNOWN_TSC_RATE
+	select X86_CUSTOM_BOOTMEDIA
 
 config USE_EXP_X86_64_SUPPORT
 	default y

src/soc/amd/genoa/Makefile.inc

diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index de996d6..164c5e9 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -1,6 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 ifeq ($(CONFIG_SOC_AMD_GENOA),y)
 
+all-y		+= mmap_boot.c
+
 bootblock-y	+= early_fch.c
 
 romstage-y	+= romstage.c

src/soc/amd/genoa/mmap_boot.c

diff --git a/src/soc/amd/genoa/mmap_boot.c b/src/soc/amd/genoa/mmap_boot.c
new file mode 100644
index 0000000..d29af41
--- /dev/null
+++ b/src/soc/amd/genoa/mmap_boot.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot_device.h>
+#include <endian.h>
+#include <spi_flash.h>
+
+#if CONFIG_ROM_SIZE >= (16 * MiB)
+#define ROM_SIZE (16 * MiB)
+#else
+#define ROM_SIZE CONFIG_ROM_SIZE
+#endif
+
+/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
+#define rom_base ((void *)(uintptr_t)(0x100000000ULL-ROM_SIZE))
+
+static const struct mem_region_device boot_dev =
+	MEM_REGION_DEV_RO_INIT(rom_base, ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+	return &boot_dev.rdev;
+}
+
+uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
+{
+	table->flash_base = 0;
+	table->host_base = (uint32_t)(uintptr_t)rom_base;
+	table->size = ROM_SIZE;
+
+	return 1;
+}