tree accb7395420f3eed18afde6b233e3e255f5c644a
parent 926d55cddd3353993604e08a7eb5d7671fd87d2f
author Subrata Banik <subratabanik@google.com> 1693492718 +0000
committer Subrata Banik <subratabanik@google.com> 1693906577 +0000

drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs

This patch refactors the existing MRC cache storing logic, which was
spread between the ROM and RAM stages, into a single early MRC cache
store stage. The only exception is when SoC user selects
FSP_NVS_DATA_POST_SILICON_INIT to store MRC cache from ramstage (after
FSP-S).

It reverts all the boot-state logic previously used to locate and store
MRC cache from NVS HOB into NVS because majority of the platform can
potentially use the early MRC cache store with improved memory caching
at the pre-RAM phase (with the ramtop implementation).

The only exception is the Xeon SP platform, which currently locates
the MRC cache post in FSP-S (at ramstage). Therefore, this patch
provides an API to the FSP 2.x silicon init code to perform late
storing of the MRC cache.

In majority cases the updated logic, the romstage (post FSP-M) will
attempt to save the MRC cache. Platform that selects
FSP_NVS_DATA_POST_SILICON_INIT config performs the same operation post
FSP-S. Depending on whether the MRC_STASH_TO_CBMEM config is
enabled, the MRC cache will either be written directly to NVRAM at the
romstage or stashed into CBMEM for a late NVRAM write at ramstage.

Below table captures the change in the boot state w/ and w/o this
patch for storing the MRC cache. Overall the goal is to ensure the
platform behavior is remain unchanged before and after this patch.

w/o this patch:

|           | Save MRC       | Finalize       | Lock the       |
|           | Cache          | MRC Cache      | Boot Medium    |
+-----------+----------------+----------------+----------------+
| MRC_WRITE | BS_OS_RESUME   | BS_OS_RESUME   | BS_ON_RESUME   |
| NV_LATE   | CHECK_ENTRY    | CHECK_ENTRY    | CHECK_EXIT     |
+-----------+----------------+----------------+----------------+
| MRC_STASH | BS_DEV         | BS_DEV         | BS_DEV         |
| TO_CBMEM  | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY|
+-----------+----------------+----------------+----------------+
| FSP_NVS   | BS_DEV_INIT    | BS_DEV         | BS_DEV         |
| DATA_POST | CHIPS_EXIT     | ENUMERATE_EXIT | RESOURCES_ENTRY|
| SILICON   |                |                |                |
| INIT      |                |                |                |
+-----------+----------------+----------------+----------------+
| Platform  | BS_PRE         | BS_DEV         | BS_DEV         |
| w/o above | DEVICE_ENTRY   | ENUMERATE_EXIT | ENUMERATE_ENTRY|
| config    |                |                |                |
| (FSP 2.0  |                |                |                |
| platforms |                |                |                |

w/ this patch:

|           | Save MRC       | Finalize       | Lock the       |
|           | Cache          | MRC Cache      | Boot Medium    |
+-----------+----------------+----------------+----------------+
| MRC_WRITE | BS_OS_RESUME   | BS_OS_RESUME   | BS_ON_RESUME   |
| NV_LATE   | CHECK_ENTRY    | CHECK_ENTRY    | CHECK_EXIT     |
+-----------+----------------+----------------+----------------+
| MRC_STASH | BS_DEV         | BS_DEV         | BS_DEV         |
| TO_CBMEM  | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY|
+-----------+----------------+----------------+----------------+
| FSP_NVS   | Post FSP-S     | BS_DEV         | BS_DEV         |
| DATA_POST | (ramstage)     | ENUMERATE_EXIT | RESOURCES_ENTRY|
| SILICON   |                |                |                |
| INIT      |                |                |                |
+-----------+----------------+----------------+----------------+
| Platform  | Post FSP-M     | BS_DEV         | BS_DEV         |
| w/o above | (romstage)     | ENUMERATE_EXIT | ENUMERATE_ENTRY|
| config    |                |                |                |
| (FSP 2.0  |                |                |                |
| platforms |                |                |                |

BUG=b:296704537
TEST=Able to build and boot google/rex without any boot time impact.

Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77556
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>