mb/google/nissa: Rework LTE GPIO configuration
Currently, the LTE pins are enabled in gpio.c, then disabled in
fw_config.c if LTE is not present. However, since there's a short delay
between mainboard_init() and fw_config_handle(), this means that when
LTE is not present GPP_H19 (SOC_I2C_SUB_INT_ODL, used for the SAR
sensor) will be floating for a short period of time.
Rework the GPIO config so that the LTE pins are disabled in the
baseboard, then enabled in fw_config.c for variants using LTE. However,
this doesn't work for WWAN_EN and WWAN_RST_L since they need to be
enabled in bootblock. So these are instead enabled in the variant
gpio.c, then disabled in fw_config.c if LTE is not present.
BUG=None
TEST=LTE still works on nivviks
Change-Id: I9d8cbdff5a0dc9bdee87ee0971bc170409d925a2
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
index 0fce609..eabb6fd 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
@@ -21,7 +21,7 @@
/* A7 : NC */
PAD_NC(GPP_A7, NONE),
/* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
- PAD_CFG_GPO(GPP_A8, 1, DEEP),
+ PAD_NC(GPP_A8, NONE),
/* A9 : ESPI_CLK ==> ESPI_SOC_CLK */
/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
/* A11 : GPP_A11 ==> EN_SPK_PA */
@@ -130,7 +130,7 @@
/* D5 : NC */
PAD_NC(GPP_D5, NONE),
/* D6 : SRCCLKREQ1# ==> WWAN_EN */
- PAD_CFG_GPO(GPP_D6, 1, DEEP),
+ PAD_NC(GPP_D6, NONE),
/* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
@@ -232,7 +232,7 @@
/* F11 : NC */
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
/* F12 : GSXDOUT ==> WWAN_RST_L */
- PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
+ PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
/* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */
PAD_CFG_GPI_INT_LOCK(GPP_F13, NONE, EDGE_BOTH, LOCK_CONFIG),
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
@@ -295,7 +295,7 @@
/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19 : SRCCLKREQ4# ==> SOC_I2C_SUB_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+ PAD_NC(GPP_H19, NONE),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 1, DEEP),
/* H21 : NC */
@@ -303,7 +303,7 @@
/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* H23 : GPP_H23 ==> WWAN_SAR_DETECT_ODL */
- PAD_CFG_GPO(GPP_H23, 1, DEEP),
+ PAD_NC(GPP_H23, NONE),
/* R0 : I2S0_SCLK ==> I2S_HP_BCLK_R */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
diff --git a/src/mainboard/google/brya/variants/nereid/gpio.c b/src/mainboard/google/brya/variants/nereid/gpio.c
index 7e70ac4..b472fe7 100644
--- a/src/mainboard/google/brya/variants/nereid/gpio.c
+++ b/src/mainboard/google/brya/variants/nereid/gpio.c
@@ -7,8 +7,6 @@
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
- /* A8 : WWAN_RF_DISABLE_ODL */
- PAD_NC(GPP_A8, NONE),
/* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */
PAD_CFG_GPO(GPP_A21, 0, DEEP),
/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
@@ -21,22 +19,13 @@
/* D3 : WCAM_RST_L */
PAD_NC(GPP_D3, NONE),
- /* D6 : WWAN_EN */
- PAD_NC(GPP_D6, NONE),
/* D15 : EN_PP2800_WCAM_X */
PAD_NC(GPP_D15, NONE),
/* D16 : EN_PP1800_PP1200_WCAM_X */
PAD_NC(GPP_D16, NONE),
- /* F12 : WWAN_RST_L */
- PAD_NC(GPP_F12, NONE),
-
- /* H19 : SOC_I2C_SUB_INT_ODL */
- PAD_NC(GPP_H19, NONE),
/* H22 : WCAM_MCLK_R */
PAD_NC(GPP_H22, NONE),
- /* H23 : WWAN_SAR_DETECT_ODL */
- PAD_NC(GPP_H23, NONE),
};
/* Early pad configuration in bootblock */
diff --git a/src/mainboard/google/brya/variants/nivviks/fw_config.c b/src/mainboard/google/brya/variants/nivviks/fw_config.c
index 4c7c626..9586213 100644
--- a/src/mainboard/google/brya/variants/nivviks/fw_config.c
+++ b/src/mainboard/google/brya/variants/nivviks/fw_config.c
@@ -6,30 +6,27 @@
#include <console/console.h>
#include <fw_config.h>
-static const struct pad_config lte_disable_pads_nivviks[] = {
+static const struct pad_config lte_enable_pads[] = {
/* A8 : WWAN_RF_DISABLE_ODL */
- PAD_NC(GPP_A8, NONE),
+ PAD_CFG_GPO(GPP_A8, 1, DEEP),
+ /* H19 : SOC_I2C_SUB_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+ /* H23 : WWAN_SAR_DETECT_ODL */
+ PAD_CFG_GPO(GPP_H23, 1, DEEP),
+};
+
+static const struct pad_config lte_disable_pads_nivviks[] = {
/* D6 : WWAN_EN */
PAD_NC(GPP_D6, NONE),
/* F12 : WWAN_RST_L */
PAD_NC(GPP_F12, NONE),
- /* H19 : SOC_I2C_SUB_INT_ODL */
- PAD_NC(GPP_H19, NONE),
- /* H23 : WWAN_SAR_DETECT_ODL */
- PAD_NC(GPP_H23, NONE),
};
static const struct pad_config lte_disable_pads_nirwen[] = {
- /* A8 : WWAN_RF_DISABLE_ODL */
- PAD_NC(GPP_A8, NONE),
/* E13 : WWAN_EN */
PAD_NC(GPP_E13, NONE),
/* F12 : WWAN_RST_L */
PAD_NC(GPP_F12, NONE),
- /* H19 : SOC_I2C_SUB_INT_ODL */
- PAD_NC(GPP_H19, NONE),
- /* H23 : WWAN_SAR_DETECT_ODL */
- PAD_NC(GPP_H23, NONE),
};
static const struct pad_config sd_disable_pads[] = {
@@ -96,7 +93,10 @@
static void fw_config_handle(void *unused)
{
- if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
+ if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
+ printk(BIOS_INFO, "Enable LTE-related GPIO pins.\n");
+ gpio_configure_pads(lte_enable_pads, ARRAY_SIZE(lte_enable_pads));
+ } else {
if (board_id() >= 2) {
printk(BIOS_INFO, "Disable LTE-related GPIO pins on nirwen.\n");
gpio_configure_pads(
diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c
index f20288f..1fdebfc 100644
--- a/src/mainboard/google/brya/variants/nivviks/gpio.c
+++ b/src/mainboard/google/brya/variants/nivviks/gpio.c
@@ -8,8 +8,12 @@
/* Pad configuration in ramstage for nivviks board_id = 0 */
static const struct pad_config board_id0_overrides[] = {
+ /* D6 : WWAN_EN */
+ PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* D7 : WLAN_CLKREQ_ODL */
PAD_NC(GPP_D7, NONE),
+ /* F12 : WWAN_RST_L */
+ PAD_CFG_GPO(GPP_F12, 1, DEEP),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
/* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
@@ -36,8 +40,12 @@
/* Pad configuration in ramstage for nivviks board_id >= 1 */
static const struct pad_config override_gpio_table[] = {
+ /* D6 : WWAN_EN */
+ PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* D7 : WLAN_CLKREQ_ODL */
PAD_NC(GPP_D7, NONE),
+ /* F12 : WWAN_RST_L */
+ PAD_CFG_GPO(GPP_F12, 1, DEEP),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
};
@@ -56,6 +64,8 @@
PAD_CFG_GPO(GPP_E13, 1, DEEP),
/* E17 : SSD_PLN_L */
PAD_CFG_GPO(GPP_E17, 1, PLTRST),
+ /* F12 : WWAN_RST_L */
+ PAD_CFG_GPO(GPP_F12, 1, DEEP),
/* H3 : WLAN_PCIE_WAKE_ODL */
PAD_NC(GPP_H3, NONE),
};