intel/sandybridge: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I5b218ce3046493b92952e47610c41b07efa4d1de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 86d1c00..ef97a1a 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -23,6 +23,7 @@
#include <elog.h>
#include <cbmem.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include "sandybridge.h"
static void sandybridge_setup_bars(void)
@@ -226,19 +227,13 @@
void northbridge_romstage_finalize(int s3resume)
{
+ struct romstage_handoff *handoff;
+
MCHBAR16(SSKPD) = 0xCAFE;
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
-
- if (s3resume) {
-
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
- }
-#endif
+ handoff = romstage_handoff_find_or_add();
+ if (handoff != NULL)
+ handoff->s3_resume = s3resume;
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
}