soc/intel/alderlake: Inform user during CSE update
If a CSE update is going to happen and early graphics is supported by
the mainboard, an on-screen text message is displayed to inform the
end user.
CSE update can take a while and an impatient end user facing a black
screen for a while may reset the device unnecessarily.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=On screen text message during CSE update observed on skolas
Change-Id: I28c4fef9345d577be287b76a2a767b5c852ec742
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72098
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc
index 7f1a94b..e8be1f5 100644
--- a/src/soc/intel/alderlake/romstage/Makefile.inc
+++ b/src/soc/intel/alderlake/romstage/Makefile.inc
@@ -5,3 +5,4 @@
romstage-y += romstage.c
romstage-y += systemagent.c
romstage-$(CONFIG_EARLY_GFX_GMA) += graphics.c
+romstage-y += ux.c
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index cf8899a..6fec2c7 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -11,10 +11,8 @@
#include <gpio.h>
#include <intelbasecode/debug_feature.h>
#include <intelblocks/cpulib.h>
-#include <intelblocks/early_graphics.h>
#include <intelblocks/pcie_rp.h>
#include <option.h>
-#include <pc80/vga.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -23,6 +21,8 @@
#include <soc/soc_chip.h>
#include <string.h>
+#include "ux.h"
+
#define FSP_CLK_NOTUSED 0xFF
#define FSP_CLK_LAN 0x70
#define FSP_CLK_FREE_RUNNING 0x80
@@ -363,17 +363,6 @@
}
}
-static void inform_user_of_memory_training(void)
-{
- if (!CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT) ||
- !early_graphics_init())
- return;
-
- printk(BIOS_INFO, "Informing user on-display of memory training.\n");
- vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE,
- "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device.");
-}
-
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
@@ -435,7 +424,7 @@
* user with an on-screen text message.
*/
if (!arch_upd->NvsBufferPtr)
- inform_user_of_memory_training();
+ ux_inform_user_of_update_operation("memory training");
config = config_of_soc();
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index 2927d12..e78f106 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -22,6 +22,8 @@
#include <string.h>
#include <security/intel/txt/txt.h>
+#include "ux.h"
+
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
@@ -126,6 +128,16 @@
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
+void cse_fw_update_misc_oper(void)
+{
+ ux_inform_user_of_update_operation("CSE update");
+}
+
+void cse_board_reset(void)
+{
+ early_graphics_stop();
+}
+
void mainboard_romstage_entry(void)
{
struct chipset_power_state *ps = pmc_get_power_state();
@@ -137,6 +149,15 @@
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
dbg_feature_cntrl_init();
+ /*
+ * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`.
+ *
+ * It would help to access VGA framebuffer prior calling into CSE
+ * firmware update or FSP-M.
+ */
+ if (!CONFIG(INTEL_TXT))
+ disable_intel_txt();
+
if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
timestamp_add_now(TS_CSE_FW_SYNC_START);
cse_fw_sync();
@@ -148,13 +169,6 @@
/* Program SMBus base address and enable it */
smbus_common_init();
- /*
- * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`.
- *
- * It would help to access VGA framebuffer prior calling into FSP-M.
- */
- if (!CONFIG(INTEL_TXT))
- disable_intel_txt();
/* Update coreboot timestamp table with CSE timestamps */
if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))
diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c
new file mode 100644
index 0000000..66b2bef
--- /dev/null
+++ b/src/soc/intel/alderlake/romstage/ux.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <intelblocks/early_graphics.h>
+#include <pc80/vga.h>
+
+#include "ux.h"
+
+void ux_inform_user_of_update_operation(const char *name)
+{
+ if (!CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT) ||
+ !early_graphics_init())
+ return;
+
+ printk(BIOS_INFO, "Informing user on-display of %s.\n", name);
+ vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE,
+ "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device.");
+}
diff --git a/src/soc/intel/alderlake/romstage/ux.h b/src/soc/intel/alderlake/romstage/ux.h
new file mode 100644
index 0000000..f09daed
--- /dev/null
+++ b/src/soc/intel/alderlake/romstage/ux.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+void ux_inform_user_of_update_operation(const char *name);