Broadwell: Synchronize for power management with FRC
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration.
BUG=chrome-os-partner:31424
TEST=Build an image, and check the procedure and recommended setting
is applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4
Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2
Original-Reviewed-on: https://chromium-review.googlesource.com/219994
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/9211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index b14ad9d..fe22bcc 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -123,6 +123,8 @@
static void root_port_init_config(device_t dev)
{
int rp;
+ u32 data;
+ u8 resp, id;
if (root_port_is_first(dev)) {
rpc.orig_rpfn = RCBA32(RPFN);
@@ -170,6 +172,15 @@
}
pcie_update_cfg(dev, 0x418, 0, 0x02000430);
+
+ /* set RP0 PCICFG E2h[5:4] = 11b before configuring ASPM */
+ if (root_port_is_first(dev)) {
+ id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07);
+ pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp);
+ data |= (0x30 << 16);
+ pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp);
+ }
+
/* Cache pci device. */
rpc.ports[rp - 1] = dev;
}