commit e2b8f30beeb1b63e1b94dccc1a96bed5c9a2c63e
author Tim Wawrzynczak <twawrzynczak@chromium.org> Mon Jul 19 15:35:47 2021 -0600
committer Tim Wawrzynczak <twawrzynczak@chromium.org> Fri Sep 10 19:38:46 2021 +0000
tree a95616939edb85010ad7dc2d679daa6518d61b15
parent 6cf79d9d14aa6be9bc5594dcf4040da8cbb87544

soc/intel/alderlake: Set LpmStateEnableMask UPD

Use the get_supported_lpm_states() function to set the respective FSP
UPD.

TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/alderlake/chip.h

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index ae85b91..5f556c8 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -116,6 +116,20 @@
 	LIMIT_AUTO       = 255,
 };
 
+/* Bit values for use in LpmStateEnableMask. */
+enum lpm_state_mask {
+	LPM_S0i2_0 = BIT(0),
+	LPM_S0i2_1 = BIT(1),
+	LPM_S0i2_2 = BIT(2),
+	LPM_S0i3_0 = BIT(3),
+	LPM_S0i3_1 = BIT(4),
+	LPM_S0i3_2 = BIT(5),
+	LPM_S0i3_3 = BIT(6),
+	LPM_S0i3_4 = BIT(7),
+	LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
+		     | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
+};
+
 struct soc_intel_alderlake_config {
 
 	/* Common struct containing soc config data required by common code */

src/soc/intel/alderlake/cpu.c

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index c5dc804..2f1ac8e 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -188,3 +188,18 @@
 
 	return ADL_UNKNOWN;
 }
+
+uint8_t get_supported_lpm_mask(void)
+{
+	enum adl_cpu_type type = get_adl_cpu_type();
+	switch (type) {
+	case ADL_M: /* fallthrough */
+	case ADL_P:
+		return LPM_S0i2_0 | LPM_S0i3_0;
+	case ADL_S:
+		return LPM_S0i2_0 | LPM_S0i2_1;
+	default:
+		printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type);
+		return 0;
+	}
+}

src/soc/intel/alderlake/fsp_params.c

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 7e1afde..107d22e 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -15,6 +15,7 @@
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
 #include <intelblocks/tcss.h>
+#include <soc/cpu.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
@@ -614,6 +615,8 @@
 	/* VrConfig Settings for IA and GT domains */
 	for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++)
 		fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]);
+
+	s_cfg->LpmStateEnableMask = get_supported_lpm_mask();
 }
 
 static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,

src/soc/intel/alderlake/include/soc/cpu.h

diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index b25979d..233e0c2 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -28,4 +28,7 @@
 
 enum adl_cpu_type get_adl_cpu_type(void);
 
+/* Get a bitmask of supported LPM states */
+uint8_t get_supported_lpm_mask(void);
+
 #endif