| commit | e2b5fee3b006f574ef27ee1e7b63735fb71858ae | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subrata.banik@intel.com> | Fri Jul 23 21:02:45 2021 +0530 |
| committer | Subrata Banik <subrata.banik@intel.com> | Wed Aug 11 05:50:02 2021 +0000 |
| tree | 057f6a87080443e63898b394e8c1ea2ffa725d75 | |
| parent | 0c6c0dac5028cf77acc0ecfe864c11812efa1039 [diff] |
arch/x86: smbios write 7 table using deterministic cache functions
This patch makes use of deterministic cache helper functions, for
example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper
functions from arch/x86/cpu_common.c file.
Also, changed argument for get_number_of_caches() function that receives
cpu_get_max_cache_share() data directly.
Drop unused variables partitions, cache_line_size and number_of_sets as
struct cpu_cache_info.size would provide the cache size directly.
TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output.
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0005, DMI type 7, 27 bytes
Cache Information
Socket Designation: CACHE1
Configuration: Enabled, Not Socketed, Level 1
Operational Mode: Unknown
Location: Internal
Installed Size: 288 kB
Maximum Size: 288 kB
Supported SRAM Types:
Unknown
Installed SRAM Type: Unknown
Speed: Unknown
Error Correction Type: Unknown
System Type: Data
Associativity: 12-way Set-associative
Handle 0x0006, DMI type 7, 27 bytes
Cache Information
Socket Designation: CACHE1
Configuration: Enabled, Not Socketed, Level 1
Operational Mode: Unknown
Location: Internal
Installed Size: 192 kB
Maximum Size: 192 kB
Supported SRAM Types:
Unknown
Installed SRAM Type: Unknown
Speed: Unknown
Error Correction Type: Unknown
System Type: Instruction
Associativity: 8-way Set-associative
Handle 0x0007, DMI type 7, 27 bytes
Cache Information
Socket Designation: CACHE2
Configuration: Enabled, Not Socketed, Level 2
Operational Mode: Unknown
Location: Internal
Installed Size: 1280 kB
Maximum Size: 1280 kB
Supported SRAM Types:
Unknown
Installed SRAM Type: Unknown
Speed: Unknown
Error Correction Type: Unknown
System Type: Unified
Associativity: Unknown
Handle 0x0008, DMI type 7, 27 bytes
Cache Information
Socket Designation: CACHE3
Configuration: Enabled, Not Socketed, Level 3
Operational Mode: Unknown
Location: Internal
Installed Size: 12288 kB
Maximum Size: 12288 kB
Supported SRAM Types:
Unknown
Installed SRAM Type: Unknown
Speed: Unknown
Error Correction Type: Unknown
System Type: Unified
Associativity: 12-way Set-associative
Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.