soc/intel/cannonlake: Add new cannon lake PCH-H support
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index cca783f..dcec9bc 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -204,6 +204,7 @@
config SOC_INTEL_I2C_DEV_MAX
int
+ default 4 if CANNONLAKE_SOC_PCH_H
default 6
# Clock divider parameters for 115200 baud rate
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 937e56c..17bcce9 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -38,6 +38,7 @@
{ CPUID_CANNONLAKE_D0, "Cannonlake D0" },
{ CPUID_COFFEELAKE_D0, "Coffeelake D0" },
{ CPUID_WHISKEYLAKE_W0, "Whiskeylake W0"},
+ { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" },
};
static struct {
@@ -49,6 +50,8 @@
{ PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)"},
{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)"},
{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)"},
+ { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" },
+ { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" },
};
static struct {
@@ -58,6 +61,8 @@
{ PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC, "Cannonlake-U Base" },
{ PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC, "Cannonlake-U Premium" },
{ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" },
+ { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" },
+ { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" },
};
static struct {
@@ -74,6 +79,8 @@
{ PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" },
{ PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2"},
{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1"},
+ { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" },
+ { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" },
};
static uint8_t get_dev_revision(pci_devfn_t dev)
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0529c5c..4049c1e 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -75,6 +75,14 @@
case PCH_DEVFN_PCIE14: return "RP14";
case PCH_DEVFN_PCIE15: return "RP15";
case PCH_DEVFN_PCIE16: return "RP16";
+ case PCH_DEVFN_PCIE17: return "RP17";
+ case PCH_DEVFN_PCIE18: return "RP18";
+ case PCH_DEVFN_PCIE19: return "RP19";
+ case PCH_DEVFN_PCIE20: return "RP20";
+ case PCH_DEVFN_PCIE21: return "RP21";
+ case PCH_DEVFN_PCIE22: return "RP22";
+ case PCH_DEVFN_PCIE23: return "RP23";
+ case PCH_DEVFN_PCIE24: return "RP24";
case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1";
case PCH_DEVFN_GSPI0: return "SPI0";
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 4d677de..63a59db 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -147,6 +147,24 @@
#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6)
#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7)
+#define PCH_DEV_SLOT_PCIE_2 0x1b
+#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0)
+#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1)
+#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2)
+#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3)
+#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4)
+#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5)
+#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6)
+#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7)
+#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0)
+#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1)
+#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2)
+#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3)
+#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4)
+#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5)
+#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6)
+#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7)
+
#define PCH_DEV_SLOT_SIO3 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)
#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1)
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index b8cddbf..6b3ccb2 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -31,7 +31,10 @@
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
m_cfg->SaGv = config->SaGv;
- m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
+ if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H))
+ m_cfg->UserBd = BOARD_TYPE_DESKTOP;
+ else
+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->RMT;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4b53117..9b8a73f 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2017 Intel Inc.
+ * Copyright 2017-2018 Intel Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -518,6 +518,7 @@
PCI_DEVICE_ID_INTEL_GLK_CSE0,
PCI_DEVICE_ID_INTEL_CNL_CSE0,
PCI_DEVICE_ID_INTEL_SKL_CSE0,
+ PCI_DEVICE_ID_INTEL_CNP_H_CSE0,
0,
};
diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c
index 365fab7..4bfe96e 100644
--- a/src/soc/intel/common/block/dsp/dsp.c
+++ b/src/soc/intel/common/block/dsp/dsp.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* * Copyright (C) 2016 Google Inc.
- * * Copyright (C) 2017 Intel Corporation.
+ * * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,6 +31,7 @@
PCI_DEVICE_ID_INTEL_CNL_AUDIO,
PCI_DEVICE_ID_INTEL_GLK_AUDIO,
PCI_DEVICE_ID_INTEL_SKL_AUDIO,
+ PCI_DEVICE_ID_INTEL_CNP_H_AUDIO,
0,
};
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 47de269..4382319 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -132,6 +132,8 @@
PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM,
PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM,
PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM,
+ PCI_DEVICE_ID_INTEL_CFL_H_GT2,
+ PCI_DEVICE_ID_INTEL_CFL_S_GT2,
0,
};
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index c6c5115..4b67280 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -213,6 +213,10 @@
PCI_DEVICE_ID_INTEL_GLK_I2C5,
PCI_DEVICE_ID_INTEL_GLK_I2C6,
PCI_DEVICE_ID_INTEL_GLK_I2C7,
+ PCI_DEVICE_ID_INTEL_CNP_H_I2C0,
+ PCI_DEVICE_ID_INTEL_CNP_H_I2C1,
+ PCI_DEVICE_ID_INTEL_CNP_H_I2C2,
+ PCI_DEVICE_ID_INTEL_CNP_H_I2C3,
0,
};
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index dbea589..bb3b4f2 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -144,6 +144,8 @@
PCI_DEVICE_ID_INTEL_CNL_BASE_U_LPC,
PCI_DEVICE_ID_INTEL_CNL_U_PREMIUM_LPC,
PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
+ PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370,
+ PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370,
0
};
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index c09c6aa..69e1f97 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -166,6 +166,7 @@
PCI_DEVICE_ID_INTEL_APL_P2SB,
PCI_DEVICE_ID_INTEL_GLK_P2SB,
PCI_DEVICE_ID_INTEL_CNL_P2SB,
+ PCI_DEVICE_ID_INTEL_CNP_H_P2SB,
0,
};
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index c4b266a..2ec37e2 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -166,6 +166,30 @@
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14,
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15,
PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23,
+ PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24,
0
};
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 0e97545..8dca629 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -126,6 +126,7 @@
PCI_DEVICE_ID_INTEL_KBP_H_PMC,
PCI_DEVICE_ID_INTEL_APL_PMC,
PCI_DEVICE_ID_INTEL_GLK_PMC,
+ PCI_DEVICE_ID_INTEL_CNP_H_PMC,
0
};
diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c
index 811d273..81fff29 100644
--- a/src/soc/intel/common/block/scs/sd.c
+++ b/src/soc/intel/common/block/scs/sd.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2017 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -69,6 +70,7 @@
PCI_DEVICE_ID_INTEL_CNL_SD,
PCI_DEVICE_ID_INTEL_GLK_SD,
PCI_DEVICE_ID_INTEL_SKL_SD,
+ PCI_DEVICE_ID_INTEL_CNP_H_SD,
0
};
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index c25cab7..62ea122 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2017 Intel Corporation.
+ * Copyright (C) 2017-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -304,6 +304,8 @@
PCI_DEVICE_ID_INTEL_KBL_U_R,
PCI_DEVICE_ID_INTEL_KBL_ID_DT,
PCI_DEVICE_ID_INTEL_CFL_ID_U,
+ PCI_DEVICE_ID_INTEL_CFL_ID_H,
+ PCI_DEVICE_ID_INTEL_CFL_ID_S,
0
};
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index d964b90..5fb7da6 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -262,6 +262,9 @@
PCI_DEVICE_ID_INTEL_GLK_UART1,
PCI_DEVICE_ID_INTEL_GLK_UART2,
PCI_DEVICE_ID_INTEL_GLK_UART3,
+ PCI_DEVICE_ID_INTEL_CNP_H_UART0,
+ PCI_DEVICE_ID_INTEL_CNP_H_UART1,
+ PCI_DEVICE_ID_INTEL_CNP_H_UART2,
0,
};
diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c
index 119decd..47a116e 100644
--- a/src/soc/intel/common/block/xdci/xdci.c
+++ b/src/soc/intel/common/block/xdci/xdci.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2017 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -41,6 +41,7 @@
PCI_DEVICE_ID_INTEL_CNL_LP_XDCI,
PCI_DEVICE_ID_INTEL_GLK_XDCI,
PCI_DEVICE_ID_INTEL_SPT_LP_XDCI,
+ PCI_DEVICE_ID_INTEL_CNP_H_XDCI,
0
};
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 0f4868a..be97aa7f 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -42,6 +42,7 @@
PCI_DEVICE_ID_INTEL_SPT_LP_XHCI,
PCI_DEVICE_ID_INTEL_SPT_H_XHCI,
PCI_DEVICE_ID_INTEL_KBP_H_XHCI,
+ PCI_DEVICE_ID_INTEL_CNP_H_XHCI,
0
};