mb/google/herobrine: NVMe id determined by logical (not physical) bit
NVMe is determined by a logical bit 1, not the physical SKU pin.
Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has
NVMe enabled on it. Previously, I thought that it was tied to a
physical pin, but this is not correct.
BUG=b:254281839
BRANCH=None
TEST=flash and boot on villager and make sure that NVMe is not
initialized in coreboot.
Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c
index c9bca73..8a51b2b 100644
--- a/src/mainboard/google/herobrine/mainboard.c
+++ b/src/mainboard/google/herobrine/mainboard.c
@@ -85,18 +85,14 @@
}
/*
- * Determine if board need to perform PCIe initialization. On Herobrine,
- * resistor strapping will be such that bit 0 will be assigned 2 (high Z) if it
- * is an NVMe enabled platform.
+ * Determine if board need to perform PCIe initialization. Will return true if
+ * NVMe initialization is needed, or false if it is an eMMC device. On
+ * Herobrine, if it is an NVMe enabled platform, logical sku_id & 2 will be
+ * true.
*/
bool mainboard_needs_pcie_init(void)
{
- /*
- * Mask out everything above the actual SKU bits We have 3 sku pins,
- * each tristate, so we can represent numbers up to 27, or 5 bits
- */
- uint32_t sku_bits_mask = 0xff;
- uint32_t sku = sku_id() & sku_bits_mask;
+ uint32_t sku = sku_id();
if (sku == CROS_SKU_UNKNOWN) {
printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku);
@@ -106,11 +102,7 @@
return true;
}
- if ((sku % 3) == 2)
- return true;
-
- /* Otherwise, eMMC */
- return false;
+ return !!(sku & 0x2);
}
static void mainboard_init(struct device *dev)