mb/**/{devicetree,overridetree}.cb: Indent with tabs

Use tabs instead of eight (sometimes less) spaces.

Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 8959a29..26207f5 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -147,19 +147,19 @@
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	register "PcieRpLtrEnable[0]" = "1"
 
-        # Root port 9 (x2)
-        #  PcieRpEnable:                 Enable root port
-        #  PcieRpClkReqSupport:          Enable CLKREQ#
-        #  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
-        #  PcieRpClkSrcNumber:           Uses 3
-        #  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
-        #  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
-        register "PcieRpEnable[8]" = "1"
-        register "PcieRpClkReqSupport[8]" = "1"
-        register "PcieRpClkReqNumber[8]" = "2"
-        register "PcieRpClkSrcNumber[8]" = "3"
-        register "PcieRpAdvancedErrorReporting[8]" = "1"
-        register "PcieRpLtrEnable[8]" = "1"
+	# Root port 9 (x2)
+	#  PcieRpEnable:                 Enable root port
+	#  PcieRpClkReqSupport:          Enable CLKREQ#
+	#  PcieRpClkReqNumber:           Uses SRCCLKREQ2#
+	#  PcieRpClkSrcNumber:           Uses 3
+	#  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
+	#  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpClkReqSupport[8]" = "1"
+	register "PcieRpClkReqNumber[8]" = "2"
+	register "PcieRpClkSrcNumber[8]" = "3"
+	register "PcieRpAdvancedErrorReporting[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
 
 	# USB 2.0
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
@@ -306,12 +306,12 @@
 				register "generic.desc" = ""WCOM Digitizer""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
 				register "generic.speed" = "I2C_SPEED_FAST_PLUS"
-                                register "generic.probed" = "1"
-                                register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
-                                register "generic.reset_delay_ms" = "20"
-                                register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
-                                register "generic.enable_delay_ms" = "1"
-                                register "generic.has_power_resource" = "1"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
 				register "generic.disable_gpio_export_in_crs" = "1"
 				register "hid_desc_reg_offset" = "0x1"
 				device i2c 0a on end