mainboard/intel/quark: Add FSP selection values
Add Kconfig values to select the FSP setup:
* FSP version: 1.1 or 2.0
* Implementation: Subroutine or SEC/PEI core based
* Build type: DEBUG or RELEASE
* Enable all debugging for FSP
* Remove USE_FSP1_1 and USE_FSP2_0
Look for include files in vendorcode/intel/fsp/fsp???/quark
BRANCH=none
BUG=None
TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2
Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
index 2acc439..0c1fe5b 100644
--- a/src/mainboard/intel/galileo/Kconfig
+++ b/src/mainboard/intel/galileo/Kconfig
@@ -18,11 +18,10 @@
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
- select CREATE_BOARD_CHECKLIST
+# select CREATE_BOARD_CHECKLIST
select ENABLE_BUILTIN_HSUART1
select HAVE_ACPI_TABLES
select SOC_INTEL_QUARK
- select USE_FSP1_1
config MAINBOARD_DIR
string
@@ -45,16 +44,107 @@
runtime. Select which generation of the Galileo that coreboot
should initialize.
-config USE_FSP1_1
- bool
- default n
+choice
+ prompt "FSP version"
+ default FSP_VERSION_1_1
+
+config FSP_VERSION_1_1
+ bool "FSP 1.1"
+ select CREATE_BOARD_CHECKLIST
select PLATFORM_USES_FSP1_1
# select ADD_FSP_RAW_BIN
-
-config USE_FSP2_0
- bool
- default n
+ help
+ Use FSP 1_1 binary
+config FSP_VERSION_2_0
+ bool "FSP 2.0"
select PLATFORM_USES_FSP2_0
select POSTCAR_STAGE
+ help
+ Use FSP 2.0 binary
+
+endchoice
+
+config FSP_VERSION
+ string
+ default "fsp1_1" if FSP_VERSION_1_1
+ default "fsp2_0" if FSP_VERSION_2_0
+
+choice
+ prompt "FSP binary type"
+ default FSP_BUILD_TYPE_DEBUG
+
+config FSP_BUILD_TYPE_DEBUG
+ bool "Debug"
+ help
+ Use the debug version of FSP
+config FSP_BUILD_TYPE_RELEASE
+ bool "Release"
+ help
+ Use the release version of FSP
+
+endchoice
+
+config FSP_BUILD_TYPE
+ string
+ default "DEBUG" if FSP_BUILD_TYPE_DEBUG
+ default "RELEASE" if FSP_BUILD_TYPE_RELEASE
+
+choice
+ prompt "FSP type"
+ depends on FSP_VERSION_2_0 || FSP_VERSION_1_1
+ default FSP_TYPE_1_1_PEI if FSP_VERSION_1_1
+ default FSP_TYPE_2_0_PEI if FSP_VERSION_2_0
+
+config FSP_TYPE_1_1
+ bool "MemInit subroutine"
+ depends on FSP_VERSION_1_1
+ help
+ FSP 1.1 implemented as subroutines, no EDK-II cores
+config FSP_TYPE_1_1_PEI
+ bool "SEC + PEI Core + MemInit PEIM"
+ depends on FSP_VERSION_1_1
+ help
+ FSP 1.1 implemented using SEC and PEI core
+config FSP_TYPE_2_0
+ bool "MemInit subroutine"
+ depends on FSP_VERSION_2_0
+ help
+ FSP 2.0 implemented as subroutines, no EDK-II cores
+config FSP_TYPE_2_0_PEI
+ bool "SEC + PEI Core + MemInit PEIM"
+ depends on FSP_VERSION_2_0
+ help
+ FSP 2.0 implemented using SEC and PEI core
+
+endchoice
+
+config FSP_TYPE
+ string
+ default "Fsp1_1" if FSP_TYPE_1_1
+ default "Fsp1_1Pei" if FSP_TYPE_1_1_PEI
+ default "Fsp2_0" if FSP_TYPE_2_0
+ default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI
+
+config FSP_DEBUG_ALL
+ bool "Enable all FSP debug support"
+ depends on FSP_VERSION_2_0 || FSP_VERSION_1_1
+ default y
+# Enable display and verification for coreboot build tests
+ select BOOTBLOCK_CONSOLE
+ select DISPLAY_HOBS
+ select DISPLAY_MTRRS
+ select DISPLAY_SMM_MEMORY_MAP
+ select DISPLAY_UPD_DATA
+ select DISPLAY_ESRAM_LAYOUT if FSP_VERSION_2_0
+ select DISPLAY_FSP_CALLS_AND_STATUS if FSP_VERSION_2_0
+ select DISPLAY_FSP_HEADER if FSP_VERSION_2_0
+ select POSTCAR_CONSOLE if FSP_VERSION_2_0
+ select VERIFY_HOBS if FSP_VERSION_2_0
+ select DISPLAY_FSP_ENTRY_POINTS if FSP_VERSION_1_1
+ help
+ Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
+ also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
+ FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
+ or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
endif # BOARD_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
index efaf007..16b2b4a 100644
--- a/src/mainboard/intel/galileo/Makefile.inc
+++ b/src/mainboard/intel/galileo/Makefile.inc
@@ -13,8 +13,8 @@
## GNU General Public License for more details.
##
-ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0)$(CONFIG_PLATFORM_USES_FSP1_1),y)
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/$(CONFIG_FSP_VERSION)/quark
endif
bootblock-y += gpio.c
diff --git a/src/soc/intel/quark/include/soc/fsp/FspEas.h b/src/soc/intel/quark/include/soc/fsp/FspEas.h
deleted file mode 100644
index 48d956e..0000000
--- a/src/soc/intel/quark/include/soc/fsp/FspEas.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/** @file
-
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPEAS_H__
-#define __FSPEAS_H__
-
-#include <fsp/upd.h>
-#include <soc/fsp/FspmUpd.h>
-#include <soc/fsp/FspsUpd.h>
-#include <soc/fsp/FsptUpd.h>
-#include <fsp/api.h>
-
-#endif /* _FSPEAS_H_ */
diff --git a/src/soc/intel/quark/include/soc/fsp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h
similarity index 97%
rename from src/soc/intel/quark/include/soc/fsp/FspUpd.h
rename to src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h
index d3277d9..cfd1ac0 100644
--- a/src/soc/intel/quark/include/soc/fsp/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspUpd.h
@@ -35,10 +35,14 @@
#include <FspEas.h>
+#pragma pack(push, 1)
+
#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */
+#pragma pack(pop)
+
#endif
diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h
similarity index 72%
rename from src/soc/intel/quark/include/soc/fsp/FspmUpd.h
rename to src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h
index a7a54a8..28e4d21 100644
--- a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspmUpd.h
@@ -35,45 +35,47 @@
#include <FspUpd.h>
+#pragma pack(push, 1)
+
/** Fsp M Configuration
**/
-struct FSP_M_CONFIG {
+typedef struct {
/** Offset 0x0040 - RmuBaseAddress
RMU microcode binary base address in SPI flash'
**/
- uint32_t RmuBaseAddress;
+ UINT32 RmuBaseAddress;
/** Offset 0x0044 - RmuLength
RMU microcode binary length in bytes
**/
- uint32_t RmuLength;
+ UINT32 RmuLength;
/** Offset 0x0048 - SerialPortBaseAddress
Debug serial port base address set by BIOS. Zero disables debug serial output.
**/
- uint32_t Reserved_48;
+ UINT32 Reserved_48;
/** Offset 0x004C - tRAS
ACT to PRE command period in picoseconds.
**/
- uint32_t tRAS;
+ UINT32 tRAS;
/** Offset 0x0050 - tWTR
Delay from start of internal write transaction to internal read command in picoseconds.
**/
- uint32_t tWTR;
+ UINT32 tWTR;
/** Offset 0x0054 - tRRD
ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.
**/
- uint32_t tRRD;
+ UINT32 tRRD;
/** Offset 0x0058 - tFAW
Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.
**/
- uint32_t tFAW;
+ UINT32 tFAW;
/** Offset 0x005C - Flags
Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN
@@ -81,155 +83,157 @@
topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices
on writes.
**/
- uint32_t Flags;
+ UINT32 Flags;
/** Offset 0x0060 - DramWidth
0=x8, 1=x16, others=RESERVED.
**/
- uint8_t DramWidth;
+ UINT8 DramWidth;
/** Offset 0x0061 - DramSpeed
0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.
**/
- uint8_t DramSpeed;
+ UINT8 DramSpeed;
/** Offset 0x0062 - DramType
0=DDR3, 1=DDR3L, others=RESERVED.
**/
- uint8_t DramType;
+ UINT8 DramType;
/** Offset 0x0063 - RankMask
bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.
**/
- uint8_t RankMask;
+ UINT8 RankMask;
/** Offset 0x0064 - ChanMask
bit[0] CHAN0_EN, others=RESERVED.
**/
- uint8_t ChanMask;
+ UINT8 ChanMask;
/** Offset 0x0065 - ChanWidth
1=x16, others=RESERVED.
**/
- uint8_t ChanWidth;
+ UINT8 ChanWidth;
/** Offset 0x0066 - AddrMode
0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.
**/
- uint8_t AddrMode;
+ UINT8 AddrMode;
/** Offset 0x0067 - SrInt
1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.
**/
- uint8_t SrInt;
+ UINT8 SrInt;
/** Offset 0x0068 - SrTemp
0=normal, 1=extended, others=RESERVED.
**/
- uint8_t SrTemp;
+ UINT8 SrTemp;
/** Offset 0x0069 - DramRonVal
0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.
**/
- uint8_t DramRonVal;
+ UINT8 DramRonVal;
/** Offset 0x006A - DramRttNomVal
0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.
**/
- uint8_t DramRttNomVal;
+ UINT8 DramRttNomVal;
/** Offset 0x006B - DramRttWrVal
0=off others=RESERVED.
**/
- uint8_t DramRttWrVal;
+ UINT8 DramRttWrVal;
/** Offset 0x006C - SocRdOdtVal
0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.
**/
- uint8_t SocRdOdtVal;
+ UINT8 SocRdOdtVal;
/** Offset 0x006D - SocWrRonVal
0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.
**/
- uint8_t SocWrRonVal;
+ UINT8 SocWrRonVal;
/** Offset 0x006E - SocWrSlewRate
0=2.5V/ns, 1=4V/ns, others=RESERVED.
**/
- uint8_t SocWrSlewRate;
+ UINT8 SocWrSlewRate;
/** Offset 0x006F - DramDensity
0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.
**/
- uint8_t DramDensity;
+ UINT8 DramDensity;
/** Offset 0x0070 - tCL
DRAM CAS Latency in clocks
**/
- uint8_t tCL;
+ UINT8 tCL;
/** Offset 0x0071 - EccScrubInterval
ECC scrub interval in miliseconds 1..255 (0 works as feature disable
**/
- uint8_t EccScrubInterval;
+ UINT8 EccScrubInterval;
/** Offset 0x0072 - EccScrubBlkSize
Number of 32B blocks read for ECC scrub 2..16
**/
- uint8_t EccScrubBlkSize;
+ UINT8 EccScrubBlkSize;
/** Offset 0x0073 - SmmTsegSize
Size of the SMM region in 1 MiB chunks
**/
- uint8_t SmmTsegSize;
+ UINT8 SmmTsegSize;
/** Offset 0x0074 - FspReservedMemoryLength
FSP reserved memory length in bytes
**/
- uint32_t FspReservedMemoryLength;
+ UINT32 FspReservedMemoryLength;
/** Offset 0x0078 - MrcDataPtr
Pointer to saved MRC data
**/
- uint32_t MrcDataPtr;
+ UINT32 MrcDataPtr;
/** Offset 0x007C - MrcDataLength
Length of saved MRC data
**/
- uint32_t MrcDataLength;
+ UINT32 MrcDataLength;
/** Offset 0x0080
**/
- uint32_t SerialPortPollForChar;
+ UINT32 SerialPortPollForChar;
/** Offset 0x0084
**/
- uint32_t SerialPortReadChar;
+ UINT32 SerialPortReadChar;
/** Offset 0x0088
**/
- uint32_t SerialPortWriteChar;
+ UINT32 SerialPortWriteChar;
/** Offset 0x008C
**/
- uint16_t UpdTerminator;
-} __attribute__((packed));
+ UINT16 UpdTerminator;
+} FSP_M_CONFIG;
/** Fsp M UPD Configuration
**/
-struct FSPM_UPD {
+typedef struct {
/** Offset 0x0000
**/
- struct FSP_UPD_HEADER FspUpdHeader;
+ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
- struct FSPM_ARCH_UPD FspmArchUpd;
+ FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040
**/
- struct FSP_M_CONFIG FspmConfig;
-} __attribute__((packed));
+ FSP_M_CONFIG FspmConfig;
+} FSPM_UPD;
+
+#pragma pack(pop)
#endif
diff --git a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h
similarity index 91%
rename from src/soc/intel/quark/include/soc/fsp/FspsUpd.h
rename to src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h
index 6b054e8..a613000 100644
--- a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FspsUpd.h
@@ -35,18 +35,22 @@
#include <FspUpd.h>
+#pragma pack(push, 1)
+
/** Fsp S UPD Configuration
**/
-struct FSPS_UPD {
+typedef struct {
/** Offset 0x0000
**/
- struct FSP_UPD_HEADER FspUpdHeader;
+ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
- uint16_t UpdTerminator;
-} __attribute__((packed));
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack(pop)
#endif
diff --git a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h
similarity index 76%
rename from src/soc/intel/quark/include/soc/fsp/FsptUpd.h
rename to src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h
index 8b1ded7..02a1e09 100644
--- a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h
@@ -35,55 +35,59 @@
#include <FspUpd.h>
+#pragma pack(push, 1)
+
/** Fsp T Common UPD
**/
-struct FSPT_COMMON_UPD {
+typedef struct {
/** Offset 0x0020
**/
- uint8_t Revision;
+ UINT8 Revision;
/** Offset 0x0021
**/
- uint8_t Reserved[3];
+ UINT8 Reserved[3];
/** Offset 0x0024
**/
- uint32_t MicrocodeRegionBase;
+ UINT32 MicrocodeRegionBase;
/** Offset 0x0028
**/
- uint32_t MicrocodeRegionLength;
+ UINT32 MicrocodeRegionLength;
/** Offset 0x002C
**/
- uint32_t CodeRegionBase;
+ UINT32 CodeRegionBase;
/** Offset 0x0030
**/
- uint32_t CodeRegionLength;
+ UINT32 CodeRegionLength;
/** Offset 0x0034
**/
- uint8_t Reserved1[12];
-} __attribute__((packed));
+ UINT8 Reserved1[12];
+} FSPT_COMMON_UPD;
/** Fsp T UPD Configuration
**/
-struct FSPT_UPD {
+typedef struct {
/** Offset 0x0000
**/
- struct FSP_UPD_HEADER FspUpdHeader;
+ FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
- struct FSPT_COMMON_UPD FsptCommonUpd;
+ FSPT_COMMON_UPD FsptCommonUpd;
/** Offset 0x0040
**/
- uint16_t UpdTerminator;
-} __attribute__((packed));
+ UINT16 UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack(pop)
#endif