Add UCB RISCV support for architecture, soc, and emulation mainboard..
Works in the RISCV version of QEMU.
Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.
We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.
Signed-off-by: Ronald G. Minnich <firstname.lastname@example.org>
Reviewed-by: Patrick Georgi <email@example.com>
Tested-by: build bot (Jenkins)
diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c
new file mode 100644
@@ -0,0 +1,9 @@
+void udelay(unsigned int n)