vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02
The headers added are generated as per FSP v3054.02.
Previous FSP version was v2503_00.
Changes Include:
- UPD Offset Update in FspmUpd.h
BUG=b:220076892
BRANCH=None
TEST=Build and boot adlnrvp
Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
index 5edd3fc..a687eb0 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h
@@ -3201,7 +3201,7 @@
/** Offset 0x0AA8 - Reserved
**/
- UINT8 Reserved45[136];
+ UINT8 Reserved45[144];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -3220,11 +3220,11 @@
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0B30
+/** Offset 0x0B38
**/
UINT8 UnusedUpdSpace34[6];
-/** Offset 0x0B36
+/** Offset 0x0B3E
**/
UINT16 UpdTerminator;
} FSPM_UPD;