This problem was introduced with
http://tracker.coreboot.org/trac/coreboot/changeset/3953
Note that all corresponding DSDTs only ever check TOM2 against 0.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl
index b3c2508..30660bb 100644
--- a/src/mainboard/gigabyte/ma78gm/dsdt.asl
+++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl
@@ -1168,7 +1168,7 @@
/* Note: Only need HID on Primary Bus */
Device(PCI0) {
External (TOM1)
- External (TOM2)
+ External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
Method(_BBN, 0) { /* Bus number = 0 */
@@ -1614,7 +1614,8 @@
/*
* If(LNotEqual(TOM2, 0x00000000)){
* Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
+ * ShiftLeft(TOM2, 20, Local0)
+ * Subtract(Local0, 0x100000000, DMHL)
* }
*/