x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index 5afae8b..cba105a 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -19,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
+#include <cpu/x86/tsc.h>
#include <arch/cpu.h>
#include <device/path.h>
#include <device/device.h>
@@ -291,4 +292,21 @@
void lb_arch_add_records(struct lb_header *header)
{
+ uint32_t freq_khz;
+ struct lb_tsc_info *tsc_info;
+
+ /* Don't advertise a TSC rate unless it's constant. */
+ if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ return;
+
+ freq_khz = tsc_freq_mhz() * 1000;
+
+ /* No use exposing a TSC frequency that is zero. */
+ if (freq_khz == 0)
+ return;
+
+ tsc_info = (void *)lb_new_record(header);
+ tsc_info->tag = LB_TAG_TSC_INFO;
+ tsc_info->size = sizeof(*tsc_info);
+ tsc_info->freq_khz = freq_khz;
}