include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSR
The new name is more consistent with the rest of the MSR definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 4e372c4..f9d20ef 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -78,7 +78,7 @@
#define LS_CFG2_MSR 0xC001102D
#define IBS_OP_DATA3_MSR 0xC0011037
#define S3_RESUME_EIP_MSR 0xC00110E0
-#define MSR_PSP_ADDR 0xc00110a2
+#define PSP_ADDR_MSR 0xc00110a2
#define MSR_PATCH_LEVEL 0x0000008B
#define CORE_PERF_BOOST_CTRL 0x15c
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 95adce4..e2f51d8 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -13,9 +13,9 @@
static uintptr_t soc_get_psp_base_address(void)
{
- uintptr_t psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
+ uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
if (!psp_mmio)
- printk(BIOS_ERR, "PSP: MSR_PSP_ADDR uninitialized\n");
+ printk(BIOS_ERR, "PSP: PSP_ADDR_MSR uninitialized\n");
return psp_mmio;
}
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 17fd9b9..d943deb 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -76,10 +76,10 @@
uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
- psp_msr = rdmsr(MSR_PSP_ADDR);
+ psp_msr = rdmsr(PSP_ADDR_MSR);
if (psp_msr.lo == 0) {
psp_msr.lo = psp_bar;
- wrmsr(MSR_PSP_ADDR, psp_msr);
+ wrmsr(PSP_ADDR_MSR, psp_msr);
}
}
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index cd14d7b..8d6290f 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -45,9 +45,9 @@
/* Determine if Bar3Hide has been set, and if hidden get the base from
* the MSR instead. */
if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
- psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
+ psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
if (!psp_mmio) {
- printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n");
+ printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n");
return 0;
}
} else {