soc/intel/xeon_sp: Add RTC failure checking
Add a weak function mainboard_rtc_failed() for mainboard customization.
Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper
triggered event.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 9589e5a..94c1764 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -6,7 +6,7 @@
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
-romstage-y += romstage.c reset.c util.c spi.c gpio.c
+romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c
postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h
index d3bad1b..49e58d3 100644
--- a/src/soc/intel/xeon_sp/include/soc/pmc.h
+++ b/src/soc/intel/xeon_sp/include/soc/pmc.h
@@ -25,6 +25,6 @@
#define GEN_PMCON_B 0xa4
#define SLP_STR_POL_LOCK (1 << 18)
#define ACPI_BASE_LOCK (1 << 17)
-
+#define RTC_BATTERY_DEAD (1 << 2)
#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h
index 42425e2..8bd5709 100644
--- a/src/soc/intel/xeon_sp/include/soc/romstage.h
+++ b/src/soc/intel/xeon_sp/include/soc/romstage.h
@@ -8,5 +8,6 @@
/* These functions are weak and can be overridden by a mainboard functions. */
void mainboard_memory_init_params(FSPM_UPD * mupd);
+void mainboard_rtc_failed(void);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c
new file mode 100644
index 0000000..9ab63a4
--- /dev/null
+++ b/src/soc/intel/xeon_sp/pmutil.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Helper functions for dealing with power management registers
+ * and the differences between PCH variants.
+ */
+
+#include <intelblocks/rtc.h>
+#include <soc/pmc.h>
+#include <soc/pci_devs.h>
+#include <device/pci.h>
+#include <console/console.h>
+
+int soc_get_rtc_failed(void)
+{
+ uint32_t pmcon_b = pci_s_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
+ int rtc_fail = !!(pmcon_b & RTC_BATTERY_DEAD);
+
+ if (rtc_fail)
+ printk(BIOS_ERR, "%s: RTC battery dead or removed\n", __func__);
+
+ return rtc_fail;
+}
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index 3db9ca9..a4853c0 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -18,6 +18,8 @@
console_init();
rtc_init();
+ if (soc_get_rtc_failed())
+ mainboard_rtc_failed();
fsp_memory_init(false);
printk(BIOS_DEBUG, "coreboot fsp_memory_init finished...\n");
@@ -47,3 +49,8 @@
{
printk(BIOS_SPEW, "WARNING: using default FSP-M parameters!\n");
}
+
+__weak void mainboard_rtc_failed(void)
+{
+
+}