| commit | e061fbf1e7837769964091cb40e75cde63fcc121 | [log] [tgz] |
|---|---|---|
| author | = <robert.chen@quanta.corp-partner.google.com> | Tue Dec 14 15:27:01 2021 +0800 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Thu Dec 23 14:31:13 2021 +0000 |
| tree | f4191903d9732f0f58d7a0a219aabe7e03e92aad | |
| parent | 0617d5a16fd38c50921c819edaeaf6962245025b [diff] |
mb/google/brya/var/vell: update overridetree for SSD setting Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 7ffc7e0..7595c6f 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -125,10 +125,10 @@ end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 0 + # Enable CPU PCIE RP 1 using CLK 1 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_req = 1, - .clk_src = 3, + .clk_src = 1, }" end device ref cnvi_wifi on