diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 63998d4..8718f97 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -170,6 +170,11 @@
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
 
+# Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection
+# in all low power states.  Cr50 TPM, if used, needs to be told to generate longer pulses.
+config TPM_CR50
+	select CR50_USE_LONG_INTERRUPT_PULSES
+
 config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_MUST_REQUEST_DISPLAY