AGESA f10 vendorcode: Remove unused sources

These fam10 sources under fam12 and fam14 were never built.

Change-Id: Iff0964aba0a061b43144427388c07aea57d6d566
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c
deleted file mode 100644
index 2190f55..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize the Family 10h specific way of running early initialization.
- *
- * Returns the table of initialization steps to perform at
- * AmdInitEarly.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE
-
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
-
-CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
-{
-  {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
-  {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
-  {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
-  {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
-  {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
-  {NULL, 0}
-};
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
- * processor that uses the standard initialization steps should take.
- *
- *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
- *
- * @param[in]       FamilyServices    The current Family Specific Services.
- * @param[out]      Table             Table of appropriate init steps for the executing core.
- * @param[in]       EarlyParams       Service Interface structure to initialize.
- * @param[in]       StdHeader         Opaque handle to standard config header.
- *
- */
-VOID
-GetF10EarlyInitOnCoreTable (
-  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
-     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
-  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
-  IN       AMD_CONFIG_PARAMS                    *StdHeader
-  )
-{
-  *Table = F10EarlyInitOnCoreTable;
-}
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c
deleted file mode 100644
index ae68a83..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 IO C-state feature support functions.
- *
- * Provides the functions necessary to initialize the IO C-state feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFeatures.h"
-#include "cpuIoCstate.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeIoCstateOnCore (
-  IN       VOID *CstateBaseMsr,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE            IoCstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable IO Cstate on a family 10h CPU.
- *
- * @param[in]    IoCstateServices   Pointer to this CPU's IO Cstate family services.
- * @param[in]    EntryPoint         Timepoint designator.
- * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- * @return       AGESA_SUCCESS      Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeIoCstate (
-  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
-  IN       UINT64                    EntryPoint,
-  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS         *StdHeader
-  )
-{
-  UINT64   LocalMsrRegister;
-  AP_TASK  TaskPtr;
-
-  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
-    // Initialize MSRC001_0073[CstateAddr] on each core to a region of
-    // the IO address map with 8 consecutive available addresses.
-    LocalMsrRegister = 0;
-
-    ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
-
-    TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
-    TaskPtr.DataTransfer.DataSizeInDwords = 2;
-    TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
-    TaskPtr.DataTransfer.DataTransferFlags = 0;
-    TaskPtr.ExeFlags = WAIT_FOR_CORE;
-    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-  }
-  return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable CState on a family 10h core.
- *
- * @param[in]    CstateBaseMsr      MSR value to write to C001_0073 as determined by core 0.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeIoCstateOnCore (
-  IN       VOID *CstateBaseMsr,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  // Initialize MSRC001_0073[CstateAddr] on each core
-  LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns the size of CST object
- *
- * @param[in]    IoCstateServices   IO Cstate services.
- * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- * @retval       CstObjSize         Size of CST Object
- *
- */
-UINT32
-STATIC
-F10GetAcpiCstObj (
-  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
-  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS         *StdHeader
-  )
-{
-  return (CST_HEADER_SIZE + CST_BODY_SIZE);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Routine to generate the C-State ACPI objects
- *
- * @param[in]      IoCstateServices       IO Cstate services.
- * @param[in]      LocalApicId            Local Apic Id for each core.
- * @param[in, out] **PstateAcpiBufferPtr  Pointer to the Acpi Buffer Pointer.
- * @param[in]      StdHeader              Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10CreateAcpiCstObj (
-  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
-  IN       UINT8                     LocalApicId,
-  IN OUT   VOID                      **PstateAcpiBufferPtr,
-  IN       AMD_CONFIG_PARAMS         *StdHeader
-  )
-{
-  UINT64            MsrData;
-  CST_HEADER_STRUCT *CstHeaderPtr;
-  CST_BODY_STRUCT   *CstBodyPtr;
-
-  // Read from MSR C0010073 to obtain CstateAddr
-  LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
-  ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
-          (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
-
-  // Typecast the pointer
-  CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
-
-  // Set CST Header
-  CstHeaderPtr->NameOpcode  = NAME_OPCODE;
-  CstHeaderPtr->CstName_a__ = CST_NAME__;
-  CstHeaderPtr->CstName_a_C = CST_NAME_C;
-  CstHeaderPtr->CstName_a_S = CST_NAME_S;
-  CstHeaderPtr->CstName_a_T = CST_NAME_T;
-
-  // Typecast the pointer
-  CstHeaderPtr++;
-  CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
-
-  // Set CST Body
-  CstBodyPtr->PkgOpcode      = PACKAGE_OPCODE;
-  CstBodyPtr->PkgLength      = CST_LENGTH;
-  CstBodyPtr->PkgElements    = CST_NUM_OF_ELEMENTS;
-  CstBodyPtr->BytePrefix     = BYTE_PREFIX_OPCODE;
-  CstBodyPtr->Count          = CST_COUNT;
-  CstBodyPtr->PkgOpcode2     = PACKAGE_OPCODE;
-  CstBodyPtr->PkgLength2     = CST_PKG_LENGTH;
-  CstBodyPtr->PkgElements2   = CST_PKG_ELEMENTS;
-  CstBodyPtr->BufferOpcode   = BUFFER_OPCODE;
-  CstBodyPtr->BufferLength   = CST_SUBPKG_LENGTH;
-  CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
-  CstBodyPtr->BufferOpcode2  = BUFFER_OPCODE;
-  CstBodyPtr->GdrOpcode      = GENERIC_REG_DESCRIPTION;
-  CstBodyPtr->GdrLength      = CST_GDR_LENGTH;
-  CstBodyPtr->AddrSpaceId    = GDR_ASI_SYSTEM_IO;
-  CstBodyPtr->RegBitWidth    = 0x08;
-  CstBodyPtr->RegBitOffset   = 0x00;
-  CstBodyPtr->AddressSize    = GDR_ASZ_BYTE_ACCESS;
-  CstBodyPtr->RegisterAddr   = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr;
-  CstBodyPtr->EndTag         = 0x0079;
-  CstBodyPtr->BytePrefix2    = BYTE_PREFIX_OPCODE;
-  CstBodyPtr->Type           = CST_C2_TYPE;
-  CstBodyPtr->WordPrefix     = WORD_PREFIX_OPCODE;
-  CstBodyPtr->Latency        = 0x4B;
-  CstBodyPtr->DWordPrefix    = DWORD_PREFIX_OPCODE;
-  CstBodyPtr->Power          = 0;
-
-  CstBodyPtr++;
-
-  //Update the pointer
-  *PstateAcpiBufferPtr = CstBodyPtr;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Routine to check whether IO Cstate should be supported.
- *
- * @param[in]      IoCstateServices      IO Cstate services.
- * @param[in]      Socket                Zero-based socket number.
- * @param[in]      StdHeader             Config Handle for library, services.
- *
- * @retval         TRUE                  Support IO Cstate.
- * @retval         FALSE                 Do not support IO Cstate.
- *
- */
-BOOLEAN
-F10IsIoCstateFeatureSupported (
-  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
-  IN       UINT32                    Socket,
-  IN       AMD_CONFIG_PARAMS         *StdHeader
-  )
-{
-  UINT64 LocalMsrRegister;
-  CPUID_DATA     CpuId;
-  CPU_LOGICAL_ID LogicalId;
-
-  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-  // Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded
-  // MSR_C001_0073 can be programmed
-  if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
-    LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
-    if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
-      LibAmdMsrRead (MSR_PATCH_LEVEL, &LocalMsrRegister, StdHeader);
-      if ((LocalMsrRegister & 0xffffffff) >= 0x010000BF) {
-        return TRUE;
-      }
-    }
-  }
-  return FALSE;
-}
-
-CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport =
-{
-  0,
-  F10IsIoCstateFeatureSupported,
-  F10InitializeIoCstate,
-  F10GetAcpiCstObj,
-  F10CreateAcpiCstObj,
-  (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
deleted file mode 100644
index 13f0aba..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
+++ /dev/null
@@ -1,1525 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  P C I    T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] =
-{
-  // Function 0
-
-// F0x68 - Link Transaction Control
-// bit[14:13], BufPriRel = 02h
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      (AMD_F10_ALL & ~AMD_F10_Dx),          // CpuRevision  rev C or less.
-    },
-    {AMD_PF_MULTI_LINK},                     // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
-      0x00004000,                           // regData
-      0x00006000,                           // regMask
-    }}
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 2
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 2
-  // 17:16 NpReqData: 2
-  // 15:12 ProbeCmd: 9
-  // 11:8 RspCmd: 9
-  // 7:5 PReq: 2
-  // 4:0 NpReqCmd: 4
-{
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_COHERENT,              // link features
-      0x10,                               // address
-      0x048A9944,                         // data
-      0x0FFFFFFF                          // mask
-    }}
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 2
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 4
-  // 4:0 NpReqCmd: 18
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_NONCOHERENT,           // link features
-      0x10,                               // address
-      0x04850292,                         // data
-      0x0FFFFFFF                          // mask
-    }}
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 0
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 6
-  // 4:0 NpReqCmd: 16
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_NONCOHERENT,           // link features
-      0x10,                               // address
-      0x008502D0,                         // data
-      0x0FFFFFFF                          // mask
-    }}
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 0
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 3
-  // 17:16 NpReqData: 2
-  // 15:12 ProbeCmd: 8
-  // 11:8 RspCmd: 9
-  // 7:5 PReq: 2
-  // 4:0 NpReqCmd: 4
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_COHERENT,              // link features
-      0x10,                               // address
-      0x008E8944,                         // data
-      0x0FFFFFFF                          // mask
-    }}
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 0
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 6
-  // 4:0 NpReqCmd: 15
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_NONCOHERENT,           // link features
-      0x10,                               // address
-      0x008502CF,                         // data
-      0x0FFFFFFF                          // mask
-    }}
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 0
-{
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_COHERENT,              // link features
-      0x14,                               // address
-      0x00000000,                         // data
-      0x1FFF0000                          // mask
-    }}
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 0
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_NONCOHERENT,           // link features
-      0x14,                               // address
-      0x00000000,                         // data
-      0x1FFF0000                          // mask
-    }}
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 1
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 1
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_COHERENT,              // link features
-      0x14,                               // address
-      0x02010000,                         // data
-      0x1FFF0000                          // mask
-    }}
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 1
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      HT_HOST_FEAT_NONCOHERENT,           // link features
-      0x14,                               // address
-      0x00010000,                         // data
-      0x1FFF0000                          // mask
-    }}
-  },
-
-// Function 3 - Misc. Control
-
-// F3x6C - Data Buffer Control
-// XBAR buffer settings
-// bits[2:0]   UpReqDBC = 2
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
-      0x00018052,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// XBAR buffer settings
-// bits[2:0]   UpReqDBC = 2
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 2
-// bits[30:28] IsocRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
-      0x00028052,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// bits[2:0]   UpReqDBC = 2
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
-      0x10018052,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 3
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 4
-// bits[22:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x00041153,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 3
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 5
-// bits[22:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x00051153,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 3
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 5
-// bits[22:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x10151153,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] DRReqCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x00081111,                           // regData
-      0x00FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] DRReqCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x00181111,                           // regData
-      0x00FF7777,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 20
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090914,                           // regData
-      0x707FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 24
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090A18,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 22
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090A16,                           // regData
-      0x707FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 23
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090917,                           // regData
-      0x707FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 23
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                          // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090917,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 21
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Dx                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090915,                           // regData
-      0x707FFF1F,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = A
-  {
-    ProcCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),  // anything but two.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00A00755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = 8
-  {
-    ProcCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),   // exactly two.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00800755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 10
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00A11755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 9
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,
-      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00911755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 5
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00511755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 1
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 7
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,
-      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00711555,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = ]
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 8
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE),     // 4 Socket, half populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00811755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 2
-// bits[23:20] FreeTok = 2
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00211755,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 1
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 6
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,
-      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00611555,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = 8
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C32_ALL                     // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00800756,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 8
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C32_ALL                     // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00811756,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000033,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 5
-// bits[7:4] ProbeTok = 1
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,              // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000015,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// All non probe filter configs
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000033,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 4
-// bits[7:4] ProbeTok = 1
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,              // Features
-      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)),     // 2 Socket, half populated, or 4 Socket, fully populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000014,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 5
-// bits[7:4] ProbeTok = 1
-  {
-    TokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,              // Features
-      (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)),     // 2 Socket, fully populated, or 4 Socket, half populated.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000015,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 5
-// bits[7:4] ProbeTok = 1
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C32_ALL                     // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      PERFORMANCE_PROBEFILTER,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000015,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_GANGED,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x000000AA,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_UNGANGED,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x00550055,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_UNGANGED,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x00550055,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 1
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_UNGANGED,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x00554055,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_NONCOHERENT,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000012A,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x000001A6,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROBEFILTER,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000016A,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 1
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x01550155,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 1
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x01550155,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 2
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_NONCOHERENT,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000022A,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 1
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 1
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x01554155,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x000001A6,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 =1
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
-      PERFORMANCE_PROBEFILTER,
-      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x00000196,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 3
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C32_ALL                     // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
-    {{
-      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEATURES_ALL,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000C0AA,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 2
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C32_ALL                     // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_NONCOHERENT,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000812A,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 2
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    HtTokenPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C32_ALL                     // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
-    {{
-      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
-      PERFORMANCE_PROFILE_ALL,
-      HT_HOST_FEAT_COHERENT,
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x000081AA,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10MultiLinkPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PackageType.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PackageType.h
deleted file mode 100644
index 76af9ac..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PackageType.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Package Type Definitions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-#ifndef _F10_PACKAGE_TYPE_H_
-#define _F10_PACKAGE_TYPE_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-// Below equates are defined to cooperate with LibAmdGetPackageType.
-#define PACKAGE_TYPE_FR2_FR5_FR6            (1 << 0)
-#define PACKAGE_TYPE_AM2R2_AM3              (1 << 1)
-#define PACKAGE_TYPE_S1G3_S1G4              (1 << 2)
-#define PACKAGE_TYPE_G34                    (1 << 3)
-#define PACKAGE_TYPE_ASB2                   (1 << 4)
-#define PACKAGE_TYPE_C32                    (1 << 5)
-
-#define PACKAGE_TYPE_FR2                    PACKAGE_TYPE_FR2_FR5_FR6
-#define PACKAGE_TYPE_FR5                    PACKAGE_TYPE_FR2_FR5_FR6
-#define PACKAGE_TYPE_FR6                    PACKAGE_TYPE_FR2_FR5_FR6
-#define PACKAGE_TYPE_S1G3                   PACKAGE_TYPE_S1G3_S1G4
-#define PACKAGE_TYPE_S1G4                   PACKAGE_TYPE_S1G3_S1G4
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-#endif  // _F10_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
deleted file mode 100644
index 394e15c..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Asymmetric Boost Initialization
- *
- * Performs the "BIOS Configuration for Asymmetric Boost" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "F10PmAsymBoostInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-SetAsymBoost (
-  IN       VOID *AsymBoostRegister,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the "Asymmetric Boost
- * Configuration" algorithm.
- *
- * The algorithm is as follows:
- *    // Determine whether the processor support boost
- *    if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) {
- *        Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0]
- *        Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1]
- *        Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2]
- *        Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3]
- *        Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4]
- *        Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5]
- *    }
- *
- * @param[in]  FamilySpecificServices  The current Family Specific Services.
- * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
- * @param[in]  StdHeader               Config handle for library and services.
- *
- */
-VOID
-F10PmAsymBoostInit (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  )
-{
-  AP_TASK                 TaskPtr;
-  UINT32                  Core;
-  UINT32                  Socket;
-  UINT32                  Module;
-  UINT32                  LocalPciRegister;
-  PCI_ADDR                PciAddress;
-  CPUID_DATA              CpuidData;
-  AGESA_STATUS            IgnoredSts;
-
-  // Check if CPB is supported. if yes, skip boosted p-state.
-  LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
-  if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
-    LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader);
-    if ((CpuidData.ECX_Reg & 0x000000FF) == 5) {
-      // get the local node ID
-      IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-      GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-      // Read F3x10C [Boost Offset]
-      PciAddress.AddressValue = F3x10C_ADDR;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-
-      TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost;
-      TaskPtr.ExeFlags = WAIT_FOR_CORE;
-      TaskPtr.DataTransfer.DataTransferFlags = 0;
-      TaskPtr.DataTransfer.DataSizeInDwords = 1;
-      TaskPtr.DataTransfer.DataPtr = &LocalPciRegister;
-      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-    }
-  }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set Asymmetric Boost.
- *
- * This function set Asymmetric Boost.
- *
- * @param[in]  AsymBoostRegister Contains the value of Asymmetric Boost register
- * @param[in]  StdHeader         Config handle for library and services
- *
- */
-VOID
-STATIC
-SetAsymBoost (
-  IN       VOID *AsymBoostRegister,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT8  ControlByte;
-  UINT32 Core;
-  UINT32 Ignored;
-  UINT64 MsrValue;
-  AGESA_STATUS IgnoredSts;
-
-  IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts);
-  ControlByte = (UINT8) ((Core & 0xFF) * 2);
-  LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
-  // Bits 5:0
-  ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
-  LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
deleted file mode 100644
index 24e99af..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Asymmetric Boost Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-#ifndef _CPU_F10_ASYM_BOOST_H_
-#define _CPU_F10_ASYM_BOOST_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmAsymBoostInit (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  );
-
-#endif  // _CPU_F10_ASYM_BOOST_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
deleted file mode 100644
index 0e8a532..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Dual-plane Only Support
- *
- * Performs the "BIOS Configuration for Dual-plane Only Support" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT32
-STATIC
-SetPstateMSR (
-  IN       VOID  *CPB,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
- *
- * The algorithm is as follows:
- *    // Determine whether algorithm applies to this processor
- *    if (CPUID Fn8000_0001_EBX[PkgType] == 0001b && (revision C or E) {
- *        // Determine whether processor is supported in this infrastructure
- *        if (((F3x1FC[DualPlaneOnly] == 1) && (this is a dual-plane platform))
- *            || ((F3x1FC[AM3r2Only] == 1) && (this is an AM3r2 platform))) {
- *            // Fixup the P-state MSRs
- *            for (each core in the system) {
- *            if (CPUID Fn8000_0007[CPB]) {
- *                Copy MSRC001_0065 as MinPstate;
- *                Copy MSRC001_0068 to MSRC001_0065;
- *                Copy MinPstate to MSRC001_0068;
- *            } else {
- *                Copy MSRC001_0068 to MSRC001_0064;
- *                Program MSRC001_0068 = 0;
- *            } // endif
- *            for (each MSR in MSRC001_00[68:64]) {
- *                if (value in MSRC001_00[68:64][IddValue] != 0) {
- *                    Set PstateEn in current MSR to 1;
- *                } // endif
- *            } // endfor
- *        } // endfor
- *        Set F3xDC[PstateMaxVal] = lowest-performance enabled P-state;
- *        Set F3xA8[PopDownPstate] = lowest-performance enabled P-state;
- *        Set F3x64[HtcPstateLimit] = lowest-performance enabled P-state;
- *        } // endif
- *    } // endif
- *
- * @param[in]  FamilySpecificServices  The current Family Specific Services.
- * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
- * @param[in]  StdHeader               Config handle for library and services.
- *
- */
-VOID
-F10PmDualPlaneOnlySupport (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  )
-{
-  AP_TASK                 TaskPtr;
-  UINT32                  CPB;
-  UINT32                  Core;
-  UINT32                  Socket;
-  UINT32                  Module;
-  UINT32                  Pvimode;
-  UINT32                  LowestPsEn;
-  UINT32                  LocalPciRegister;
-  UINT32                  ActiveCores;
-  UINT32                  ProcessorPackageType;
-  PCI_ADDR                PciAddress;
-  CPUID_DATA              CpuidData;
-  CPU_LOGICAL_ID          LogicalId;
-  AGESA_STATUS            IgnoredSts;
-
-  // get the local node ID
-  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
-  // get the package type
-  ProcessorPackageType = LibAmdGetPackageType (StdHeader);
-  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-  if (((LogicalId.Revision & (AMD_F10_Cx | AMD_F10_Ex)) != 0) && ((ProcessorPackageType & PACKAGE_TYPE_AM2R2_AM3) != 0)) {
-    PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-    PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
-    LibAmdPciRead (AccessWidth32, PciAddress, &Pvimode, StdHeader);
-    if ((((LocalPciRegister & 0x80000000) != 0) && (((POWER_CTRL_MISC_REGISTER *) &Pvimode)->PviMode == 0))
-      || ((LocalPciRegister & 0x04000000) != 0)) {
-      CPB = 0;
-      LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
-      if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
-        CPB = 1;
-      }
-
-      TaskPtr.FuncAddress.PfApTaskIO = SetPstateMSR;
-      TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
-      TaskPtr.DataTransfer.DataTransferFlags = 0;
-      TaskPtr.DataTransfer.DataSizeInDwords = 1;
-      TaskPtr.DataTransfer.DataPtr = &CPB;
-
-      GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
-      for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
-        ApUtilRunCodeOnSocketCore ((UINT8)0, (UINT8)Core, &TaskPtr, StdHeader);
-      }
-      LowestPsEn = ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
-
-      PciAddress.AddressValue = CPTC2_PCI_ADDR;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = LowestPsEn;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-
-      PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((POPUP_PSTATE_REGISTER *) &LocalPciRegister)->PopDownPstate = LowestPsEn;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-
-      PciAddress.AddressValue = HTC_PCI_ADDR;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = LowestPsEn;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-    }
-  }
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set P-State MSR.
- *
- * This function set the P-state MSRs per each core in the system.
- *
- * @param[in]  CPB               Contains the value of Asymmetric Boost register
- * @param[in]  StdHeader         Config handle for library and services
- *
- * @return         Return the lowest-performance enabled P-state
- */
-UINT32
-STATIC
-SetPstateMSR (
-  IN       VOID  *CPB,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32 dtemp;
-  UINT32 LowestPsEn;
-  UINT64 MsrValue;
-  UINT64 MinMsrValue;
-
-  if (*(UINT32*) CPB != 0) {
-    LibAmdMsrRead (MSR_PSTATE_1, &MinMsrValue, StdHeader);
-    LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
-    LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
-    LibAmdMsrWrite (MSR_PSTATE_4, &MinMsrValue, StdHeader);
-  } else {
-    LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
-    LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
-    MsrValue = 0;
-    LibAmdMsrWrite (MSR_PSTATE_4, &MsrValue, StdHeader);
-  }
-
-  LowestPsEn = 0;
-  for (dtemp = MSR_PSTATE_0; dtemp <= MSR_PSTATE_4; dtemp++) {
-    LibAmdMsrRead (dtemp, &MsrValue, StdHeader);
-    if (((PSTATE_MSR *) &MsrValue)->IddValue != 0) {
-      MsrValue = MsrValue | BIT63;
-      LibAmdMsrWrite (dtemp, &MsrValue, StdHeader);
-      LowestPsEn =  dtemp - MSR_PSTATE_0;
-    }
-  }
-  return (LowestPsEn);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
deleted file mode 100644
index 941bcf4..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BIOS Configuration for Dual-plane Only Support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-#ifndef _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-#define _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmDualPlaneOnlySupport (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  );
-
-#endif  // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
deleted file mode 100644
index 63e9232..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB COF VID Initialization
- *
- * Performs the "BIOS Northbridge COF and VID Configuration" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44702 $   @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuApicUtilities.h"
-#include "OptionMultiSocket.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10Utilities.h"
-#include "F10PmNbCofVidInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// Structure used for performing the steps outlined in
-/// the NB COFVID configuration sequence
-typedef struct {
-  UINT8   NewNbVid;           ///< Destination NB VID code
-  BOOLEAN NbVidUpdateAll;     ///< Status of NbVidUpdateAll
-} NB_COF_VID_INIT_WARM;
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-PmNbCofVidInitP0P1Core (
-  IN       VOID *NewNbVid,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-VOID
-STATIC
-PmNbCofVidInitWarmCore (
-  IN       VOID *FunctionData,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the "Northbridge COF and
- * VID Configuration" algorithm.
- *
- * The steps are as follows:
- *    1. Determine if the algorithm is necessary by checking if all NB FIDs
- *       match in the coherent fabric.  If so, check to see if NbCofVidUpdate
- *       is zero for all CPUs.  If that is also true, no further steps are
- *       necessary.  If not + cold reset, proceed to step 2.  If not + warm
- *       reset, proceed to step 8.
- *    2. Determine NewNbVid & NewNbFid.
- *    3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
- *    4. Copy NewNbVid to P0 NbVid on all local cores.
- *    5. Transition to P1 on all local cores.
- *    6. Transition to P0 on local core 0 only.
- *    7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
- *    8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
- *       on all local cores.
- *    9. Transition to Startup Pstate on all local cores.
- *
- * @param[in]  FamilySpecificServices  The current Family Specific Services.
- * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
- * @param[in]  StdHeader               Config handle for library and services.
- *
- */
-VOID
-F10PmNbCofVidInit (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  )
-{
-  BOOLEAN   PerformNbCofVidCfg;
-  BOOLEAN   NotUsed;
-  BOOLEAN   SystemNbCofsMatch;
-  UINT8     NewNbFid;
-  UINT8     NewNbVid;
-  UINT32    Socket;
-  UINT32    Module;
-  UINT32    Core;
-  UINT32    SystemNbCof;
-  UINT32    AndMask;
-  UINT32    OrMask;
-  UINT32    Ignored;
-  UINT32    NewNbVoltage;
-  UINT32    FrequencyDivisor;
-  WARM_RESET_REQUEST Request;
-  AP_TASK   TaskPtr;
-  PCI_ADDR  PciAddress;
-  AGESA_STATUS IgnoredSts;
-  NB_COF_VID_INIT_WARM FunctionData;
-
-  PerformNbCofVidCfg = TRUE;
-  OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader);
-  if (SystemNbCofsMatch) {
-    if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
-      PerformNbCofVidCfg = FALSE;
-    }
-  }
-  if (PerformNbCofVidCfg) {
-    // get the local node ID
-    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
-    ASSERT (Core == 0);
-
-    // get NewNbVid
-    FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
-                                             &CpuEarlyParamsPtr->PlatformConfig,
-                                             &PciAddress,
-                                             (UINT32) 0,
-                                             &Ignored,
-                                             &Ignored,
-                                             &NewNbVoltage,
-                                             StdHeader);
-    ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
-    NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
-    ASSERT (NewNbVid < 0x80);
-
-    if (!(IsWarmReset (StdHeader))) {
-
-      // determine NewNbFid
-      NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
-
-      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
-      TaskPtr.DataTransfer.DataSizeInDwords = 1;
-      TaskPtr.DataTransfer.DataPtr = &NewNbVid;
-      TaskPtr.DataTransfer.DataTransferFlags = 0;
-      TaskPtr.ExeFlags = 0;
-      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-
-      // Transition core 0 to P0 and wait for change to complete
-      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
-
-      PciAddress.Address.Register = CPTC0_REG;
-      AndMask = 0xFFFFFFFF;
-      ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
-      OrMask = 0x00000000;
-      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
-      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
-      ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
-      // warm reset request
-      GetWarmResetFlag (StdHeader, &Request);
-      Request.RequestBit = TRUE;
-      Request.StateBits = Request.PostStage - 1;
-      SetWarmResetFlag (StdHeader, &Request);
-    } else {
-      // warm reset path
-
-      FunctionData.NewNbVid = NewNbVid;
-      FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
-
-      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
-      TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
-      TaskPtr.DataTransfer.DataPtr = &FunctionData;
-      TaskPtr.DataTransfer.DataTransferFlags = 0;
-      TaskPtr.ExeFlags = WAIT_FOR_CORE;
-      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-    }
-  } // skip whole algorithm
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Cold reset support routine for F10PmNbCofVidInit.
- *
- * This function implements steps 3, 4, & 5 on each core.
- *
- * @param[in]  NewNbVid           NewNbVid determined by core 0 in step 2.
- * @param[in]  StdHeader          Config handle for library and services.
- *
- */
-VOID
-STATIC
-PmNbCofVidInitP0P1Core (
-  IN       VOID *NewNbVid,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT8  NumBoostStates;
-  UINT32 MsrAddress;
-  UINT64 LocalMsrRegister;
-  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-  NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-  LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
-  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &LocalMsrRegister)->StartupPstate) + PS_REG_BASE);
-  LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
-  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1 + NumBoostStates), &LocalMsrRegister, StdHeader);
-  ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = *(UINT8 *) NewNbVid;
-  LibAmdMsrWrite (PS_REG_BASE + NumBoostStates, &LocalMsrRegister, StdHeader);
-  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Warm reset support routine for F10PmNbCofVidInit.
- *
- * This function implements steps 8 & 9 on each core.
- *
- * @param[in]  FunctionData       Contains NewNbVid determined by core 0 in step
- *                                2, and NbVidUpdateAll.
- * @param[in]  StdHeader          Config handle for library and services.
- *
- */
-VOID
-STATIC
-PmNbCofVidInitWarmCore (
-  IN       VOID *FunctionData,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32 MsrAddress;
-  UINT64 LocalMsrRegister;
-  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-  for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
-    LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &LocalMsrRegister)->IddValue != 0) {
-      if ((((PSTATE_MSR *) &LocalMsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
-        ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
-        LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
-      }
-    }
-  }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
deleted file mode 100644
index ab10da6..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB COF VID Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
-#define _CPU_F10_PM_NB_COF_VID_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmNbCofVidInit (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  );
-
-#endif  // _CPU_F10_PM_NB_COF_VID_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
deleted file mode 100644
index 19a8217..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB Pstate Initialization
- *
- * Performs the action described in F3x1F0[NbPstate] as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuApicUtilities.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "F10PmNbPstateInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// Structure used for modifying the P-state
-/// MSRs on fuse enable CPUs.
-typedef struct {
-  UINT8   NbVid1;             ///< Destination NB VID code
-  UINT8   NbPstate;           ///< Status of NbVidUpdateAll
-} NB_PSTATE_INIT;
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-PmNbPstateInitCore (
-  IN       VOID *NbPstateParams,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the actions described in the
- * description of F3x1F0[NbPstate].
- *
- * If F3x1F0[NbPstate] is non zero, it specifies the highest performance
- * P-state in which to enable NbDid.  Each core must loop through their
- * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
- *
- * @param[in]  FamilySpecificServices  The current Family Specific Services.
- * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
- * @param[in]  StdHeader               Config handle for library and services.
- *
- */
-VOID
-F10PmNbPstateInit (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  )
-{
-  UINT32         Core;
-  UINT32         Module;
-  UINT32         LocalPciRegister;
-  UINT32         Socket;
-  AP_TASK        TaskPtr;
-  PCI_ADDR       PciAddress;
-  AGESA_STATUS   IgnoredSts;
-  NB_PSTATE_INIT ApParams;
-
-  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
-    if (CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) {
-      IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-      ASSERT (Core == 0);
-      GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = 0x1F0;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      if ((LocalPciRegister & 0x00070000) != 0) {
-        ApParams.NbPstate = (UINT8) ((LocalPciRegister & 0x00070000) >> 16);
-        ASSERT (ApParams.NbPstate < NM_PS_REG);
-
-        PciAddress.Address.Function = FUNC_4;
-        PciAddress.Address.Register = 0x1F4;
-        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-        ApParams.NbVid1 = (UINT8) ((LocalPciRegister & 0x00003F80) >> 7);
-
-        TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
-        TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
-        TaskPtr.DataTransfer.DataPtr = &ApParams;
-        TaskPtr.DataTransfer.DataTransferFlags = 0;
-        TaskPtr.ExeFlags = WAIT_FOR_CORE;
-        ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-
-      }
-    }
-  }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Support routine for F10PmNbPstateInit.
- *
- * This function modifies NbVid and NbDid on each core.
- *
- * @param[in]  NbPstateParams     Appropriate NbVid1 and NbPstate as determined by core 0.
- * @param[in]  StdHeader          Config handle for library and services.
- *
- */
-VOID
-STATIC
-PmNbPstateInitCore (
-  IN       VOID *NbPstateParams,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32 MsrAddress;
-  UINT64 LocalMsrRegister;
-
-  for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
-    LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
-    if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
-      ((PSTATE_MSR *) &LocalMsrRegister)->NbDid = 1;
-      ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
-      LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
-    }
-  }
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
deleted file mode 100644
index 652f2fb..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB P-State Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
-#define _CPU_F10_PM_NB_PSTATE_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                 D E F I N I T I O N S     A N D     M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- *                        F U N C T I O N    P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmNbPstateInit (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
-  IN       AMD_CONFIG_PARAMS     *StdHeader
-  );
-
-#endif  // _CPU_F10_PM_NB_PSTATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
deleted file mode 100644
index 74481a3..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
+++ /dev/null
@@ -1,2237 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  P C I    T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] =
-{
-// F0x68 - Link Transaction Control
-// bit[14:13], BufPriRel = 01b
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                     // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
-      0x00002000,                           // regData
-      0x00006000,                           // regMask
-    }}
-  },
-// F0x68 - Link Transaction Control
-// bit[24], DispRefModeEn = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    {AMD_PF_ALL},                             // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
-      0x00000000,                           // regData
-      0x01000000,                           // regMask
-    }}
-  },
-// F0x68 - Link Transaction Control
-// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset.
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    {AMD_PF_UMA},                     // platform Features
-    {{
-      PERFORMANCE_IS_WARM_RESET,
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
-      0x01000000,                           // regData
-      0x01000000,                           // regMask
-    }}
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 2
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 4
-  // 4:0 NpReqCmd: 18
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x10,                                 // Address
-      0x04850292,                           // Data
-      0x0FFFFFFF                            // Mask
-    }},
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 2
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 4
-  // 4:0 NpReqCmd: 18
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x10,                                 // Address
-      0x04850292,                           // Data
-      0x0FFFFFFF                            // Mask
-    }},
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 2
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 3
-  // 4:0 NpReqCmd: 11
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x10,                                 // Address
-      0x0485026B,                           // Data
-      0x0FFFFFFF                            // Mask
-    }},
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 2
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 6
-  // 4:0 NpReqCmd: 15
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x10,                                 // Address
-      0x008502CF,                           // Data
-      0x0FFFFFFF                            // Mask
-    }},
-  },
-  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
-  // 27:25 FreeData: 0
-  // 24:20 FreeCmd: 8
-  // 19:18 RspData: 1
-  // 17:16 NpReqData: 1
-  // 15:12 ProbeCmd: 0
-  // 11:8 RspCmd: 2
-  // 7:5 PReq: 6
-  // 4:0 NpReqCmd: 15
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x10,                                 // Address
-      0x808502CF,                           // Data
-      0x0FFFFFFF                            // Mask
-    }},
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 0
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x14,                                 // Address
-      0x00000000,                           // Data
-      0x1FFF0000                            // Mask
-    }},
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 0
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x14,                                 // Address
-      0x00000000,                           // Data
-      0x1FFF0000                            // Mask
-    }},
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 1
-  // 18:16 IsocNpReqCmd: 7
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x14,                                 // Address
-      0x000F0000,                           // Data
-      0x1FFF0000                            // Mask
-    }},
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 1
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x14,                                 // Address
-      0x00010000,                           // Data
-      0x1FFF0000                            // Mask
-    }},
-  },
-  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
-  // 28:27 IsocRspData: 0
-  // 26:25 IsocNpReqData: 0
-  // 24:22 IsocRspCmd: 0
-  // 21:19 IsocPReq: 0
-  // 18:16 IsocNpReqCmd: 1
-  {
-    HtHostPciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },
-    {{
-      HT_HOST_FEATURES_ALL,                 // Link Features
-      0x14,                                 // Address
-      0x00010000,                           // Data
-      0x1FFF0000                            // Mask
-    }},
-  },
-// F0x170 - Link Extended Control Register - Link 0, sublink 0
-// bit[8] LS2En = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_ALL                           // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                     // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
-      0x00000100,                           // regData
-      0x00000100,                           // regMask
-    }}
-  },
-// F2x118 - Memory Controller Configuration Low Register
-// bits[13:12] MctPriIsoc = 10b
-// bits[31:28] MctVarPriCntLmt = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
-      0x00002000,                           // regData
-      0xF0003000,                           // regMask
-    }}
-  },
-// F2x118 - Memory Controller Configuration Low Register
-// bits[13:12] MctPriIsoc = 00b
-// bits[31:28] MctVarPriCntLmt = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },        // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
-      0x00000000,                           // regData
-      0xF0000000,                           // regMask
-    }}
-  },
-// F2x118 - Memory Controller Configuration Low Register
-// bits[13:12] MctPriIsoc = 11b
-// bits[31:28] MctVarPriCntLmt = 1
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },       // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
-      0x10003000,                           // regData
-      0xF0003000,                           // regMask
-    }}
-  },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32  0
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
-      0x00000000,                           // regData
-      0x00000400,                           // regMask
-    }}
-  },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 = 0
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
-      0x00000000,                           // regData
-      0x00000400,                           // regMask
-    }}
-  },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 = 1
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
-      0x00000400,                           // regData
-      0x00000400,                           // regMask
-    }}
-  },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 = 1
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
-      0x00000400,                           // regData
-      0x00000400,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// bits[2:0]   UpReqDBC = 2
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
-      0x00018052,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// bits[2:0]   UpReqDBC = 1
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 6
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
-      0x60018051,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// bits[2:0]   UpReqDBC = 2
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
-      0x10018052,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// bits[2:0]   UpReqDBC = 1
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 6
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
-      0x60018051,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x6C - Data Buffer Control
-// bits[2:0]   UpReqDBC = 2
-// bits[5:4]   DnReqDBC = 1
-// bits[7:6]   DnRspDBC = 1
-// bit[15]     DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
-      0x10018052,                           // regData
-      0x700780F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 3
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 4
-// bits[22:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x00041153,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 2
-// bits[22:20] IsocReqCBC = 2
-// bits[26:24] IsocPreqCBC = 1
-// bits[30:28] IsocRspCBC = 6
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x61221151,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 2
-// bits[22:20] IsocReqCBC = 2
-// bits[26:24] IsocPreqCBC = 1
-// bits[30:28] IsocRspCBC = 6
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x61221151,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 3
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 4
-// bits[22:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[30:28] IsocRspCBC = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x11141153,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0]   UpReqCBC = 3
-// bits[5:4]   DnReqCBC = 1
-// bits[7:6]   DnRspCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 5
-// bits[22:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
-      0x10151153,                           // regData
-      0x777777F7,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[31:28] DRReqCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x00081111,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 9
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x91180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 9
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x91180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 1
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC =1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 0
-// bits[31:28] DRReqCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x00181111,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 8
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,  // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x81180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 8
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,  // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x81180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 7
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,  // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x71180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 7
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,  // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x71180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = C
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xC1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = C
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xC1181111,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = F
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xF1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = F
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xF1181111,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = B
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xB1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = B
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xB1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = A
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xA1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = A
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xA1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = E
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xE1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = E
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xE1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = D
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xD1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = D
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0xD1180101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0]   UpReqCBC = 1
-// bits[6:4]   DnReqCBC = 0
-// bits[10:8]  UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 8
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
-      0x01880101,                           // regData
-      0xF7FF7777,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 20
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090914,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0]  Xbar2SriFreeListCBC = 15
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080F,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0]  Xbar2SriFreeListCBC = 15
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080F,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 12
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080C,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 12
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080C,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 9
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070809,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 9
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070809,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 17
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070811,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090900,                           // regData
-      0x007FFF00,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 18
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),  // 3 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090912,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 16
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE),  // 4 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00090910,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 14
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0009090E,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 12
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0009090C,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0]  Xbar2SriFreeListCBC = 14
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080E,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0]  Xbar2SriFreeListCBC = 14
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080E,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0]  Xbar2SriFreeListCBC = 13
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080D,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0]  Xbar2SriFreeListCBC = 13
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080D,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 11
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080B,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 11
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080B,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 10
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080A,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 10
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080A,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 8
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070808,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 8
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070808,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 7
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070807,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 7
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070807,                           // regData
-      0x007FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 16
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x00070810,                           // regData
-      0x707FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 15
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
-    {{
-      PERFORMANCE_PROFILE_ALL,
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
-      0x0007080F,                           // regData
-      0x707FFF1F,                           // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      PERFORMANCE_NO_L3_CACHE,
-      (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
-      0x00000016,                               // regData
-      0x0000001F,                               // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 20, 2-core is 20
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      PERFORMANCE_NO_L3_CACHE,
-      (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
-      0x00000014,                               // regData
-      0x0000001F,                               // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18.
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      PERFORMANCE_NO_L3_CACHE,
-      (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
-      0x00000012,                               // regData
-      0x0000001F,                               // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16.
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      PERFORMANCE_NO_L3_CACHE,
-      (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
-      0x00000010,                               // regData
-      0x0000001F,                               // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14.
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      PERFORMANCE_NO_L3_CACHE,
-      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
-      0x0000000E,                               // regData
-      0x0000001F,                               // regMask
-    }}
-  },
-// F3x7C - Free List Buffer Count
-// bits[4:0]  Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12.
-  {
-    CoreCountsPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      PERFORMANCE_NO_L3_CACHE,
-      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
-      0x0000000C,                               // regData
-      0x0000001F,                               // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = 8
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00800756,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 3
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 3
-// bits[23:20] FreeTok = 12
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00C37756,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 3
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 3
-// bits[23:20] FreeTok = 12
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00C37756,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 2
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 3
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 3
-// bits[23:20] FreeTok = 12
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00C37656,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 8
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
-      0x00815756,                           // regData
-      0x00F3FFFF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000033,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 6
-// bits[7:4] ProbeTok = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000036,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 6
-// bits[7:4] ProbeTok = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000036,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 6
-// bits[7:4] ProbeTok = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000036,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
-      0x00000033,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 3
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000C0AA,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 1
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 2
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x8000152A,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 1
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 2
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x8000152A,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 3
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0000C0AA,                           // regData
-      0xD5FFFFFF,                           // regMask
-    }}
-  },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 2
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 3
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
-      0x0500852A,                           // regData
-      0xC000FFFF,                           // regMask
-    }}
-  },
-  // F3x158 - Link to XCS Token Count Registers
-  // bits [3:0]LnkToXcsDRToken = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU) },
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
-      0x00000000,
-      0x0000000F
-    }}
-  },
-  // F3x158 - Link to XCS Token Count Registers
-  // bits [3:0]LnkToXcsDRToken = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_ALL                         // CpuRevision
-    },
-    { (AMD_PF_UMA_IFCM | AMD_PF_UMA) },
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
-      0x00000003,
-      0x0000000F
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10SingleLinkPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
deleted file mode 100644
index 182a554..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Cache Flush On Halt Function.
- *
- * Contains code to initialize Cache Flush On Halt feature for Family 10h BL.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10/BL
- * @e \$Revision: 44737 $   @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- *----------------------------------------------------------------------------
- */
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          P U B L I C     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *    Enable BL-C Cpu Cache Flush On Halt Function
- *
- *    @param[in]       FamilySpecificServices   The current Family Specific Services.
- *    @param[in]       EntryPoint               Timepoint designator.
- *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
- *    @param[in]       StdHeader                Config Handle for library, services.
- */
-VOID
-SetF10BlCacheFlushOnHaltRegister (
-  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
-  IN       UINT64                       EntryPoint,
-  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS            *StdHeader
-  )
-{
-  UINT32       AndMask;
-  UINT32       OrMask;
-  UINT32       CoreCount;
-  PCI_ADDR     PciAddress;
-  CPU_LOGICAL_ID        CpuFamilyRevision;
-
-  if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
-    GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
-    PciAddress.Address.Function = FUNC_3;
-    PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
-    if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
-      // F3xDC[25:19] = 04h
-      // F3xDC[18:16] = 111b
-      AndMask = 0xFC00FFFF;
-      OrMask = 0x00270000;
-    } else {
-      // F3xDC[25:19] = 28h
-      // F3xDC[18:16] = 111b
-      AndMask = 0xFC00FFFF;
-      OrMask = 0x01470000;
-
-      //For BL_C2 single Core, F3xDC[18:16] = 0
-      GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
-      if (CoreCount == 1) {
-        if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
-          OrMask = 0x01400000;
-        }
-      }
-    }
-
-    // Get the Or Mask value from IDS
-    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
-    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
-  }
-}
-
-CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
-{
-  0,
-  SetF10BlCacheFlushOnHaltRegister
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
deleted file mode 100644
index 0851500..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
-{
-  0x1052, 0x1041,
-  0x1053, 0x1043
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns the appropriate microcode patch equivalent ID table.
- *
- *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[out]  BlEquivalenceTablePtr    Points to the first entry in the table.
- *  @param[out]  NumberOfElements         Number of valid entries in the table.
- *  @param[in]   StdHeader                Header for library and services.
- *
- */
-VOID
-GetF10BlMicrocodeEquivalenceTable (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-     OUT   CONST VOID **BlEquivalenceTablePtr,
-     OUT   UINT8 *NumberOfElements,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
-  *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
deleted file mode 100644
index c33f8a9..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  HT  Phy   T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
-{
-
-//
-// NOTE: This entry is here for making this array not to be empty.
-//       This entry should be removed after adding another.
-//
-//
-// Deemphasis Settings
-//
-
-// For BL-C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis            00h        00h          00h     0                0             0             0
-// -3dB postcursor          12h        00h          00h     1                0             0             0
-// -6dB postcursor          1Fh        00h          00h     1                0             0             0
-// -8dB postcursor          1Fh        06h          00h     1                1             0             1
-// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
-// -11dB postcursor with
-// -8dB precursor           1Fh        06h          07h     1                1             1             1
-
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_BL_C3                         // CpuRevision
-    },
-    {AMD_PF_ALL},                             // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL_NONE,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x00000080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10BlHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
deleted file mode 100644
index 72e29cf..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] =
-{
-  {
-    0x1052,
-    AMD_F10_BL_C2
-  },
-  {
-    0x1053,
-    AMD_F10_BL_C3
-  }
-};
-
-VOID
-GetF10BlLogicalIdAndRev (
-     OUT   CONST CPU_LOGICAL_ID_XLAT **BlIdPtr,
-     OUT   UINT8 *NumberOfElements,
-     OUT   UINT64 *LogicalFamily,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
-  *BlIdPtr = CpuF10BlLogicalIdAndRevArray;
-  *LogicalFamily = AMD_FAMILY_10_BL;
-}
-
-//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev =
-//{
-//  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
-//  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
-//};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
deleted file mode 100644
index 5392f4f..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches;
-
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns a table containing the appropriate microcode patches.
- *
- *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[out]  BlUcodePtr               Points to the first entry in the table.
- *  @param[out]  NumberOfElements         Number of valid entries in the table.
- *  @param[in]   StdHeader                Header for library and services.
- *
- */
-VOID
-GetF10BlMicroCodePatchesStruct (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-     OUT   CONST VOID **BlUcodePtr,
-     OUT   UINT8 *NumberOfElements,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = CpuF10BlNumberOfMicrocodePatches;
-  *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
deleted file mode 100644
index 660f653..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] =
-{
-//  M S R    T a b l e s
-// ----------------------
-//
-// NOTE: This entry is here for making this array not to be empty.
-//       This entry should be removed after adding another.
-//
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_B0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MSR_LS_CFG,                           // MSR Address
-      0x0000000000000000,                   // OR Mask
-      (1 << 1),                             // NAND Mask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = {
-  AllCores,
-  (sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  (TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
deleted file mode 100644
index 7ed16aa..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  P C I    T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
-{
-  // Function 0
-
-// F0x16C - Link Global Extended Control Register, Errata 351
-// bit[15:13] ForceFullT0 = 0
-// bit[5:0] T0Time = 0x14
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_BL_C2                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x00000014,                           // regData
-      0x0000E03F,                           // regMask
-    }}
-  },
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_BL_C3                       // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x00000040,                           // regData
-      0x000000C0,                           // regMask
-    }}
-  },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_BL_C3                      // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x0000C226,                           // regData
-      0x0000E23F,                           // regMask
-    }}
-  },
-// F0x170 - Link Extended Control Register - Link 0, sublink 0
-// Errata 351 (only need to override single link case.)
-// bit[8] LS2En = 0,
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_BL_C2                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
-      0x00000000,                           // regData
-      0x00000100,                           // regMask
-    }}
-  },
-
-
-// F3x80 - ACPI Power State Control
-// ACPI FIDVID Change
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 1
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 0
-  {
-    HtFeatPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_BL_Cx                       // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      HT_HOST_FEATURES_ALL,                 // link feats
-      PACKAGE_TYPE_S1G3_S1G4,               // package type
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
-      0x000B0000,                           // regData
-      0x00FF0000,                           // regMask
-    }}
-  },
-// F3xA0 - Power Control Miscellaneous
-// bits[28] NbPstateForce = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_BL_C3                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
-      0x10000000,                           // regData
-      0x10000000,                           // regMask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10BlPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
deleted file mode 100644
index fd32024..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Cache Flush On Halt Function.
- *
- * Contains code to initialize Cache Flush On Halt feature for Family 10h DA.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10/DA
- * @e \$Revision: 44737 $   @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- *----------------------------------------------------------------------------
- */
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          P U B L I C     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *    Enable DA-C Cpu Cache Flush On Halt Function
- *
- *    @param[in]       FamilySpecificServices   The current Family Specific Services.
- *    @param[in]       EntryPoint               Timepoint designator.
- *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
- *    @param[in]       StdHeader                Config Handle for library, services.
- */
-VOID
-SetF10DaCacheFlushOnHaltRegister (
-  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
-  IN       UINT64                       EntryPoint,
-  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS            *StdHeader
-  )
-{
-  UINT32       CoreCount;
-  UINT32       AndMask;
-  UINT32       OrMask;
-  PCI_ADDR     PciAddress;
-  CPU_LOGICAL_ID LogicalId;
-
-  if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
-    // F3xDC[25:19] = 04h
-    // F3xDC[18:16] = 111b
-    PciAddress.Address.Function = FUNC_3;
-    PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
-    AndMask = 0xFC00FFFF;
-    OrMask = 0x00270000;
-
-    GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-    if (LogicalId.Revision == AMD_F10_DA_C2) {
-      //For DA_C2 single Core, F3xDC[18:16] = 0
-      GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
-      if (CoreCount == 1) {
-        OrMask = 0x00200000;
-      }
-    }
-
-    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
-    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
-  }
-}
-
-CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt =
-{
-  0,
-  SetF10DaCacheFlushOnHaltRegister
-};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
deleted file mode 100644
index 6fd6b6f..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
-{
-  0x1062, 0x1062,
-  0x1063, 0x1043
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns the appropriate microcode patch equivalent ID table.
- *
- *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[out]  DaEquivalenceTablePtr    Points to the first entry in the table.
- *  @param[out]  NumberOfElements         Number of valid entries in the table.
- *  @param[in]   StdHeader                Header for library and services.
- *
- */
-VOID
-GetF10DaMicrocodeEquivalenceTable (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-     OUT   CONST VOID **DaEquivalenceTablePtr,
-     OUT   UINT8 *NumberOfElements,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
-  *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
deleted file mode 100644
index bdbb09c..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  HT   Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] =
-{
-
-//
-// Deemphasis Settings
-//
-
-// For DA, also set [7]TxLs23ClkGateEn.
-//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis            00h        00h          00h     0                0             0             0
-// -3dB postcursor          12h        00h          00h     1                0             0             0
-// -6dB postcursor          1Fh        00h          00h     1                0             0             0
-// -8dB postcursor          1Fh        06h          00h     1                1             0             1
-// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
-// -11dB postcursor with
-// -8dB precursor           1Fh        06h          07h     1                1             1             1
-
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL_NONE,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x00000080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL_NONE,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0x00000080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__3,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x80120080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__3,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0x80120080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__6,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x801F0080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__6,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0x801F0080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__8,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0xC01F06C0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__8,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0xC01F06C0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0xC01F0DC0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0xC01F0DC0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11_8,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0xE01F06C7,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C2                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11_8,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0xE01F06C7,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10DaHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
deleted file mode 100644
index ca1e6dc..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] =
-{
-  {
-    0x1062,
-    AMD_F10_DA_C2
-  },
-  {
-    0x1063,
-    AMD_F10_DA_C3
-  }
-};
-
-VOID
-GetF10DaLogicalIdAndRev (
-     OUT   CONST CPU_LOGICAL_ID_XLAT **DaIdPtr,
-     OUT   UINT8 *NumberOfElements,
-     OUT   UINT64 *LogicalFamily,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
-  *DaIdPtr = CpuF10DaLogicalIdAndRevArray;
-  *LogicalFamily = AMD_FAMILY_10_DA;
-}
-
-//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev =
-//{
-//  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
-//  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
-//};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
deleted file mode 100644
index 6d1b2df..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns a table containing the appropriate microcode patches.
- *
- *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[out]  DaUcodePtr               Points to the first entry in the table.
- *  @param[out]  NumberOfElements         Number of valid entries in the table.
- *  @param[in]   StdHeader                Header for library and services.
- *
- */
-VOID
-GetF10DaMicroCodePatchesStruct (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-     OUT   CONST VOID **DaUcodePtr,
-     OUT   UINT8 *NumberOfElements,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = CpuF10DaNumberOfMicrocodePatches;
-  *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
deleted file mode 100644
index 99e0b58..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] =
-{
-//  M S R    T a b l e s
-// ----------------------
-//
-// NOTE: This entry is here for making this array not to be empty.
-//       This entry should be removed after adding another.
-//
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_B0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MSR_LS_CFG,                           // MSR Address
-      0x0000000000000000,                   // OR Mask
-      (1 << 1),                             // NAND Mask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = {
-  AllCores,
-  (sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  (TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
deleted file mode 100644
index 26aab9b..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  P C I    T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] =
-{
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_DA_ALL                      // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x00000040,                           // regData
-      0x000000C0,                           // regMask
-    }}
-  },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_DA_ALL                      // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x0000C226,                           // regData
-      0x0000E23F,                           // regMask
-    }}
-  },
-// F3x80 - ACPI Power State Control
-// ACPI FIDVID Change
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 1
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 0
-  {
-    HtFeatPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_DA_Cx                       // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      HT_HOST_FEATURES_ALL,                 // link feats
-      PACKAGE_TYPE_S1G3_S1G4,               // package type
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
-      0x000B0000,                           // regData
-      0x00FF0000,                           // regMask
-    }}
-  },
-// F3xA0 - Power Control Miscellaneous
-// bits[13:11] PllLockTime = 1
-// bits[28] NbPstateForce = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_DA_ALL                      // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
-      0x10000800,                           // regData
-      0x10003800,                           // regMask
-    }}
-  },
-// F3xD4 - Clock Power/Timing Control 0 Register
-// bits[30:28] NbClkDiv = 5
-  {
-    HtFeatPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_DA_C2                       // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      HT_HOST_FEAT_HT3,                     // link feats
-      PACKAGE_TYPE_S1G3_S1G4,               // package type
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
-      0x50000000,                           // regData
-      0x70000000,                           // regMask
-    }}
-  },
-// F3x188 - NB Extended Configuration Low Register
-// bits[4] EnStpGntOnFlushMaskWakeup = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_DA_Cx                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
-      0x00000010,                           // regData
-      0x00000010,                           // regMask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10DaPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
deleted file mode 100644
index 225fda5..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
+++ /dev/null
@@ -1,1036 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/REVC
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 01000085 for 1040 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 =
-{{
-0x08,
-0x20,
-0x01,
-0x05,
-0x85,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xc1,
-0xb9,
-0x5d,
-0x3d,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x40,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x2f,
-0x02,
-0x00,
-0x00,
-0xa0,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xcf,
-0xf8,
-0xff,
-0x2a,
-0xc3,
-0x3f,
-0xd5,
-0xfd,
-0xbc,
-0xff,
-0xff,
-0xb3,
-0x0f,
-0xff,
-0x58,
-0xd5,
-0xf0,
-0x35,
-0x95,
-0x03,
-0x1d,
-0xf8,
-0x63,
-0x7b,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x80,
-0x77,
-0xff,
-0x7f,
-0xfe,
-0xe1,
-0x98,
-0x8a,
-0x54,
-0xfe,
-0xaf,
-0xff,
-0xff,
-0x87,
-0x7f,
-0xa9,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x1f,
-0xc0,
-0x65,
-0xf4,
-0x0d,
-0xf0,
-0xe0,
-0x8f,
-0xfe,
-0x04,
-0xde,
-0x04,
-0x03,
-0xad,
-0xc3,
-0x2f,
-0xfe,
-0xa9,
-0xfc,
-0x07,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0x15,
-0x00,
-0xb0,
-0x00,
-0xf8,
-0xaf,
-0xe4,
-0x3f,
-0x07,
-0xf8,
-0x79,
-0xf8,
-0xfe,
-0xff,
-0x97,
-0xa7,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0xbf,
-0xf1,
-0x00,
-0xfe,
-0x7f,
-0x6f,
-0x80,
-0x03,
-0x4a,
-0x1a,
-0x00,
-0xc8,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xc3,
-0x3f,
-0x80,
-0x7f,
-0xfc,
-0x7f,
-0x0f,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x03,
-0x00,
-0xff,
-0xdf,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xfb,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfd,
-0x6b,
-0x00,
-0xa0,
-0xcf,
-0x56,
-0x0e,
-0x80,
-0xe0,
-0x0f,
-0xe8,
-0x75,
-0xf6,
-0xff,
-0xff,
-0x00,
-0xc3,
-0xbb,
-0x16,
-0xf2,
-0x04,
-0x37,
-0xf8,
-0x13,
-0x0e,
-0x7f,
-0x0c,
-0xb8,
-0xe0,
-0xdc,
-0x35,
-0x00,
-0x60,
-0xff,
-0xff,
-0x1f,
-0x7f,
-0x78,
-0xc7,
-0xa2,
-0x95,
-0xff,
-0xe9,
-0x3f,
-0xdf,
-0xe0,
-0xcf,
-0x2a,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0xff,
-0xf2,
-0xbf,
-0xff,
-0xfd,
-0x1f,
-0xfc,
-0x7b,
-0x0f,
-0xc0,
-0x23,
-0xd0,
-0xed,
-0xf5,
-0xe0,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xfe,
-0x03,
-0xf9,
-0x5f,
-0x01,
-0x7e,
-0x1e,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x4c,
-0x06,
-0x00,
-0xbc,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
deleted file mode 100644
index 07e89d6..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
+++ /dev/null
@@ -1,1036 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c6 for 1041 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/REVC
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c6 for 1041 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6 =
-{{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc6,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xb5,
-0x66,
-0x0e,
-0x84,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x41,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0xa0,
-0x09,
-0x00,
-0x00,
-0xa5,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xa1,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x97,
-0xd1,
-0x7f,
-0x00,
-0x83,
-0x3f,
-0x36,
-0xc0,
-0xa0,
-0x1b,
-0xf8,
-0x13,
-0x0e,
-0xbf,
-0x0c,
-0xb4,
-0xf2,
-0x1f,
-0xf8,
-0xa7,
-0x3c,
-0xfc,
-0x03,
-0xfc,
-0x40,
-0x03,
-0x54,
-0x00,
-0x92,
-0xff,
-0xe0,
-0xbf,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x5f,
-0x9e,
-0xfa,
-0xff,
-0x9f,
-0x87,
-0x7f,
-0x80,
-0x03,
-0xf8,
-0xff,
-0xc6,
-0x01,
-0x0e,
-0xfc,
-0xbd,
-0x00,
-0xa0,
-0x2a,
-0x69,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x00,
-0x5a,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0x1c,
-0x9c,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0xf0,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0x5c,
-0x56,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x00,
-0x61,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xfb,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfd,
-0x6b,
-0x00,
-0xa0,
-0xff,
-0xfe,
-0xff,
-0xcb,
-0xf0,
-0xef,
-0xf5,
-0x7f,
-0x8f,
-0x40,
-0x3f,
-0x00,
-0x83,
-0xbf,
-0xb7,
-0xd7,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe4,
-0x7f,
-0xf9,
-0x0f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf0,
-0x32,
-0x19,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
deleted file mode 100644
index b8fb5ff..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
+++ /dev/null
@@ -1,1036 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c7 for 1062 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/REVC
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c7 for 1062 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7 =
-{{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc7,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xb8,
-0x53,
-0x63,
-0x1d,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x62,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x9a,
-0x0b,
-0x00,
-0x00,
-0x16,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x6f,
-0x58,
-0x39,
-0x00,
-0x81,
-0x3f,
-0xa0,
-0xd7,
-0x04,
-0x00,
-0xfc,
-0xb7,
-0x0f,
-0xff,
-0x58,
-0xf7,
-0x72,
-0xc0,
-0xff,
-0x6f,
-0x3c,
-0xfc,
-0x03,
-0xfc,
-0xc0,
-0x18,
-0xd5,
-0x00,
-0x80,
-0xff,
-0x66,
-0x3c,
-0xeb,
-0xc0,
-0x9f,
-0xd9,
-0x4d,
-0xee,
-0xf8,
-0xff,
-0xff,
-0x83,
-0x7f,
-0xa6,
-0x07,
-0xe8,
-0xff,
-0xff,
-0xe8,
-0x1f,
-0xbe,
-0xb5,
-0x00,
-0x60,
-0x2f,
-0x6a,
-0xbf,
-0xe8,
-0x04,
-0xff,
-0xf5,
-0xf3,
-0xf0,
-0xaf,
-0x7a,
-0x00,
-0xff,
-0xd9,
-0x31,
-0xc0,
-0x83,
-0x3f,
-0xff,
-0x03,
-0x88,
-0xff,
-0x58,
-0xc8,
-0x0f,
-0xef,
-0x35,
-0x00,
-0xd0,
-0x00,
-0xfb,
-0xbf,
-0x85,
-0xff,
-0x03,
-0xd8,
-0x72,
-0xf8,
-0xad,
-0x1c,
-0x80,
-0xfb,
-0x1f,
-0xc0,
-0xe7,
-0xa0,
-0xbe,
-0x71,
-0x00,
-0x86,
-0x7f,
-0x40,
-0xaf,
-0x07,
-0xff,
-0x1e,
-0x00,
-0xf8,
-0x6f,
-0x95,
-0x03,
-0x50,
-0xf4,
-0x03,
-0xf8,
-0x1c,
-0xf8,
-0xff,
-0x3f,
-0x00,
-0xf0,
-0xee,
-0x84,
-0xfc,
-0xfe,
-0xff,
-0xff,
-0x22,
-0xc3,
-0x1f,
-0x51,
-0x96,
-0x50,
-0x16,
-0x0d,
-0x00,
-0xf8,
-0xfe,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe5,
-0xa6,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfa,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x3f,
-0xe3,
-0x3e,
-0x0f,
-0xfd,
-0x50,
-0x03,
-0xb0,
-0xdf,
-0x8c,
-0xf9,
-0x3c,
-0xf4,
-0x43,
-0x0e,
-0xc0,
-0xfd,
-0x32,
-0xe5,
-0xf3,
-0xd0,
-0x0f,
-0x03,
-0x00,
-0xfb,
-0x24,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xff,
-0xff,
-0x00,
-0xfd,
-0xbb,
-0x14,
-0xf2,
-0xc3,
-0x2f,
-0xf8,
-0x13,
-0xcc,
-0x7f,
-0x0c,
-0xb8,
-0x0e,
-0x74,
-0xf5,
-0x03,
-0xf0,
-0xf8,
-0x33,
-0x03,
-0x1c,
-0x2b,
-0xd7,
-0x00,
-0x00,
-0xeb,
-0xe5,
-0x1f,
-0x80,
-0xc0,
-0x1f,
-0x1b,
-0xe0,
-0x9e,
-0x9b,
-0x7f,
-0x00,
-0x03,
-0x7f,
-0x6c,
-0x80,
-0xf8,
-0x7d,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe0,
-0x6d,
-0x62,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x00,
-0xfa,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0xe0,
-0xfc,
-0xff,
-0x3f,
-0xcb,
-0xf0,
-0x8f,
-0x75,
-0xff,
-0xe5,
-0xff,
-0xff,
-0x2c,
-0xc3,
-0x3f,
-0xd6,
-0xf5,
-0x1c,
-0xf0,
-0xff,
-0x8b,
-0x0f,
-0xff,
-0x00,
-0x3f,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe0,
-0xbf,
-0x18,
-0x0f,
-0x3a,
-0xf0,
-0x27,
-0xf6,
-0xd1,
-0x35,
-0xfe,
-0x7f,
-0xe7,
-0xe1,
-0x9f,
-0xe8,
-0x5f,
-0xc6,
-0xff,
-0xff,
-0xeb,
-0x87,
-0x7f,
-0xaf,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0xbf,
-0xad,
-0x03,
-0x3c,
-0xf8,
-0x13,
-0x1f,
-0xc0,
-0x7f,
-0xf6,
-0x45,
-0xff,
-0xf0,
-0xad,
-0xff,
-0x04,
-0xff,
-0xff,
-0x83,
-0xad,
-0xc3,
-0x2f,
-0x04,
-0x00,
-0x2c,
-0x80,
-0xfe,
-0x03,
-0xf8,
-0xff,
-0xb5,
-0xe8,
-0x1f,
-0xbe,
-0xff,
-0xdf,
-0x65,
-0xfc,
-0x07,
-0x38,
-0x6b,
-0xf8,
-0xee,
-0xbf,
-0x96,
-0xff,
-0x5f,
-0xeb,
-0xff,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0xb5,
-0xfc,
-0xbf,
-0x5a,
-0x57,
-0x0e,
-0xbf,
-0xad,
-0x07,
-0xf0,
-0xf4,
-0x13,
-0xf9,
-0x3c,
-0xf8,
-0x80,
-0x3f,
-0x81,
-0xf0,
-0xcb,
-0x60,
-0xeb,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0xb7,
-0xf5,
-0x00,
-0x07,
-0x7f,
-0x62,
-0x80,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1f,
-0xbe,
-0xb5,
-0xe8,
-0x60,
-0x7c,
-0xc0,
-0x9f,
-0x75,
-0xf8,
-0x65,
-0xb0,
-0x00,
-0x04,
-0x90,
-0x00,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
deleted file mode 100644
index 2807a5d..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
+++ /dev/null
@@ -1,1036 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c8 for 1043 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/REVC
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c8 for 1043 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8 =
-{{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc8,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x6a,
-0x99,
-0x77,
-0xef,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x43,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x10,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x18,
-0x80,
-0x38,
-0xc0,
-0x83,
-0x37,
-0x80,
-0xff,
-0xb8,
-0xff,
-0xff,
-0x13,
-0x0e,
-0xbf,
-0x0c,
-0xb6,
-0x7a,
-0xc4,
-0xff,
-0x2f,
-0x3c,
-0xfc,
-0x6b,
-0xfd,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x97,
-0xff,
-0xff,
-0xff,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x00,
-0xfe,
-0xbf,
-0xf5,
-0x9f,
-0x87,
-0x7e,
-0x22,
-0x01,
-0xc6,
-0x00,
-0xc4,
-0x7c,
-0x1e,
-0xfa,
-0x01,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x70,
-0x59,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0xec,
-0x93,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0x70,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0xac,
-0x5c,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x00,
-0x5e,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0x20,
-0x04,
-0xff,
-0xbf,
-0xe8,
-0xf0,
-0xaf,
-0xf5,
-0xf3,
-0xff,
-0xd9,
-0x7a,
-0x00,
-0x83,
-0x3f,
-0x31,
-0xc0,
-0x0c,
-0x7d,
-0xe3,
-0x00,
-0x0f,
-0xfe,
-0x80,
-0x5e,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0x65,
-0xfe,
-0xff,
-0x9f,
-0x7f,
-0xf8,
-0xc7,
-0xba,
-0x96,
-0xf2,
-0xff,
-0x7f,
-0xfa,
-0xe1,
-0x1f,
-0xeb,
-0x45,
-0x0e,
-0xf8,
-0xff,
-0x9f,
-0x87,
-0x7f,
-0x80,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0x5f,
-0x8c,
-0x7b,
-0x1d,
-0xf8,
-0x13,
-0xbf,
-0xe8,
-0x1a,
-0xff,
-0xf4,
-0xf3,
-0xf0,
-0x4f,
-0xff,
-0x2f,
-0xe3,
-0xff,
-0xd7,
-0xf5,
-0xc3,
-0xbf,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xd6,
-0x03,
-0xf8,
-0xdf,
-0x89,
-0x01,
-0x1e,
-0xfc,
-0xfb,
-0x0f,
-0xe0,
-0x3f,
-0xd6,
-0xa2,
-0x7f,
-0xf8,
-0xff,
-0x7f,
-0x82,
-0xff,
-0x97,
-0xc1,
-0xd6,
-0xe1,
-0x40,
-0x02,
-0x00,
-0x14,
-0x7f,
-0xff,
-0x01,
-0xfc,
-0xdf,
-0x5a,
-0xf4,
-0x0f,
-0xfe,
-0xff,
-0xef,
-0x32,
-0xfc,
-0x03,
-0x9c,
-0x35,
-0x7f,
-0xf7,
-0x5f,
-0xcb,
-0xf0,
-0xaf,
-0xf5,
-0xff,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x5a,
-0x87,
-0x5f,
-0xad,
-0x2b,
-0xf8,
-0xdf,
-0xd6,
-0x03,
-0x1e,
-0xfa,
-0x89,
-0x7c,
-0x20,
-0x7d,
-0xc0,
-0x9f,
-0x75,
-0xf8,
-0x65,
-0xb0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0xdb,
-0x7a,
-0xc0,
-0x83,
-0x3f,
-0x31,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xf4,
-0x0f,
-0xdf,
-0x5a,
-0x4f,
-0xa0,
-0x3e,
-0xe0,
-0xd8,
-0x3a,
-0xfc,
-0x32,
-0x00,
-0xc0,
-0x01,
-0x48,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
deleted file mode 100644
index fb7fc89..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  HT   Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
-{
-// 0x60:0x68
-  {
-    HtPhyRangeRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_C0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL0_ALL,               //
-      0x60, 0x68,                           // Address range
-      0x00000040,                           // regData
-      0x00000040,                           // regMask
-    }}
-  },
-// 0x70:0x78
-  {
-    HtPhyRangeRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_C0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL1_ALL,               //
-      0x70, 0x78,                           // Address range
-      0x00000040,                           // regData
-      0x00000040,                           // regMask
-    }}
-  },
-// Erratum 354
-// 0x40:48
-  {
-    HtPhyRangeRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      (AMD_F10_C2 | AMD_F10_C3)           // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0x40, 0x48,                           // Address
-      0x00000040,                           // regData
-      0x00000040,                           // regMask
-    }}
-  },
-// 0x50:0x58
-  {
-    HtPhyRangeRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      (AMD_F10_C2 | AMD_F10_C3)          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0x50, 0x58,                           // Address
-      0x00000040,                           // regData
-      0x00000040,                           // regMask
-    }}
-  },
-// 0xC0
-  {
-    HtPhyRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL0_ALL,               //
-      0xC0,                                 // Address
-      0x40040000,                           // regData
-      0xe01F0000,                           // regMask
-    }}
-  },
-// 0xD0
-  {
-    HtPhyRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL1_ALL,               //
-      0xD0,                                 // Address
-      0x40040000,                           // regData
-      0xe01F0000,                           // regMask
-    }}
-  },
-// 0xCF
-// FIFO_PTR_OPT_VALUE
-  {
-    HtPhyProfileRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                         // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      PERFORMANCE_NB_PSTATES_ENABLE,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xCF,                                 // Address
-      0x0000004A,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// 0xDF
-// FIFO_PTR_OPT_VALUE
-  {
-    HtPhyProfileRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                         // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      PERFORMANCE_NB_PSTATES_ENABLE,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xDF,                                 // Address
-      0x0000004A,                           // regData
-      0x000000FF,                           // regMask
-    }}
-  },
-// 0x520A
-  {
-    HtPhyRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                           // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL0_ALL,                   //
-      0x520A,                               // Address
-      0x00004000,                           // regData
-      0x00006000,                           // regMask
-    }}
-  },
-// 0x530A
-  {
-    HtPhyRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                           // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL1_ALL,                   //
-      0x530A,                               // Address
-      0x00004000,                           // regData
-      0x00006000,                           // regMask
-    }}
-  },
-
-
-
-
-//
-// Deemphasis Settings
-//
-
-// For C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis            00h        00h          00h     0                0             0             0
-// -3dB postcursor          12h        00h          00h     1                0             0             0
-// -6dB postcursor          1Fh        00h          00h     1                0             0             0
-// -8dB postcursor          1Fh        06h          00h     1                1             0             1
-// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
-// -11dB postcursor with
-// -8dB precursor           1Fh        06h          07h     1                1             1             1
-
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL_NONE,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x00000080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL_NONE,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0x00000080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__3,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x80120080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__3,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0x80120080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__6,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0x801F0080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__6,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0x801F0080,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__8,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0xC01F06C0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__8,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0xC01F06C0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0xC01F0DC0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0xC01F0DC0,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11_8,
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0xC5,                                 // Address
-      0xE01F06C7,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-  {
-    DeemphasisRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C3                               // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      DEEMPHASIS_LEVEL__11_8,
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0xD5,                                 // Address
-      0xE01F06C7,                           // regData
-      0xE01F1FDF,                           // regMask
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10RevCHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
deleted file mode 100644
index 3400e2a..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 HW C1e feature support functions.
- *
- * Provides the functions necessary to initialize the hardware C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuHwC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeHwC1eOnCore (
-  IN       VOID *IntPendMsr,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Should hardware C1e be enabled
- *
- * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- * @retval       TRUE               HW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsHwC1eSupported (
-  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  CPU_LOGICAL_ID LogicalId;
-
-  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-
-  if (((LogicalId.Revision & AMD_F10_RB_ALL) & ~(AMD_F10_RB_C3)) != 0) {
-    return FALSE;
-  }
-  return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable Hardware C1e on a family 10h CPU.
- *
- * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
- * @param[in]    EntryPoint         Timepoint designator.
- * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- * @return       AGESA_SUCCESS      Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeHwC1e (
-  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
-  IN       UINT64 EntryPoint,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32 C1eData;
-  UINT64 LocalMsrRegister;
-  AP_TASK TaskPtr;
-
-  LocalMsrRegister = 0;
-  C1eData     = PlatformConfig->C1ePlatformData;
-
-  if (PlatformConfig->C1eMode == C1eModeAuto) {
-    C1eData = PlatformConfig->C1ePlatformData3;
-  }
-
-  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = C1eData;
-  ((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 1;
-  ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 1;
-  ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
-
-  TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
-  TaskPtr.DataTransfer.DataSizeInDwords = 2;
-  TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
-  TaskPtr.DataTransfer.DataTransferFlags = 0;
-  TaskPtr.ExeFlags = WAIT_FOR_CORE;
-  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
-  return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable Hardware C1e on a family 10h core.
- *
- * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeHwC1eOnCore (
-  IN       VOID *IntPendMsr,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT64  LocalMsrRegister;
-
-  // Enable C1e
-  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
-
-  // Set OS Visible Workaround Status BIT1 to indicate that C1e
-  // is enabled.
-  LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
-  LocalMsrRegister |= BIT1;
-  LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
-}
-
-
-CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
-{
-  0,
-  F10IsHwC1eSupported,
-  F10InitializeHwC1e
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
deleted file mode 100644
index 2fbe6e5..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
-{
-//  M S R    T a b l e s
-// ----------------------
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_B0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MSR_LS_CFG,                           // MSR Address
-      0x0000000000000000,                   // OR Mask
-      (1 << 1),                             // NAND Mask
-    }}
-  },
-
-// MSR_BU_CFG (0xC0011023)
-// bit[21] = 1
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_B0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MSR_BU_CFG,                           // MSR Address
-      (1 << 21),                            // OR Mask
-      (1 << 21),                            // NAND Mask
-    }}
-  },
-
-// MSR_BU_CFG2 (0xC001102A)
-// bit[50] = 1
-// For GH rev C1 and later [RdMmExtCfgQwEn]=1
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_C0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MSR_BU_CFG2,                          // MSR Address
-      0x0004000000000000,                   // OR Mask
-      0x0004000000000000,                   // NAND Mask
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
-  AllCores,
-  (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
deleted file mode 100644
index f1b6cd5..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/RevC
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  P C I    T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
-{
-// Function 2 - DRAM Controller
-
-// F2x1B0 - Extended Memory Controller Configuration Low Register
-//
-// bit[5:4], AdapPrefNegativeStep = 0
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
-      0x00000000,                           // regData
-      0x00000030,                           // regMask
-    }}
-  },
-// Function 3 - Misc. Control
-
-// F3x158 - Link to XCS Token Count
-// bits[3:0] LnkToXcsDRToken = 3
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_GT_A2                       // CpuRevision
-    },
-    {AMD_PF_UMA},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
-      0x00000003,                           // regData
-      0x0000000F,                           // regMask
-    }}
-  },
-// F3x80 - ACPI Power State Control
-// ACPI State C2
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 1
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
-      0x0000E681,                           // regData
-      0x0000FFFF,                           // regMask
-    }}
-  },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
-  {
-    HtFeatPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      HT_HOST_FEAT_HT1,                     // link feats
-      PACKAGE_TYPE_ASB2,                    // package type
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
-      0x00008700,                           // regData
-      0x0000FF00,                           // regMask
-    }}
-  },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 1
-// bits[7:5] ClkDivisor = 7
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_C3                           // CpuRevision
-    },
-    {AMD_PF_ALL},                             // platformFeatures
-    {{
-      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
-      0x0000F600,                           // regData
-      0x0000FF00,                           // regMask
-    }}
-  },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
-  {
-    HtFeatPciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      HT_HOST_FEAT_HT1,                     // link feats
-      PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2),  // package type
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
-      0x00008700,                           // regData
-      0x0000FF00,                           // regMask
-    }}
-  },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
-      0x00005000,                           // regData
-      0x00007000,                           // regMask
-    }}
-  },
-// F3x180 - NB Extended Configuration
-// bits[23] SyncFloodOnDramTempErr = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
-      0x00800000,                           // regData
-      0x00800000,                           // regMask
-    }}
-  },
-// F3x188 - NB Extended Configuration Low Register
-// bit[22] = DisHldReg2
-// Errata #346
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_Cx                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
-      0x00400000,                           // regData
-      0x00400000,                           // regMask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10RevCPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
deleted file mode 100644
index 898de9f..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 SW C1e feature support functions.
- *
- * Provides the functions necessary to initialize the software C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuSwC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeSwC1eOnCore (
-  IN       VOID *IntPendMsr,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  );
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Should software C1e be enabled
- *
- * @param[in]    SwC1eServices      Pointer to this CPU's SW C1e family services.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- * @retval       TRUE               SW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsSwC1eSupported (
-  IN       SW_C1E_FAMILY_SERVICES *SwC1eServices,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable Software C1e on a family 10h CPU.
- *
- * @param[in]    SwC1eServices      Pointer to this CPU's SW C1e family services.
- * @param[in]    EntryPoint         Timepoint designator.
- * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- * @return       AGESA_SUCCESS      Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeSwC1e (
-  IN       SW_C1E_FAMILY_SERVICES *SwC1eServices,
-  IN       UINT64 EntryPoint,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT64 LocalMsrRegister;
-  AP_TASK TaskPtr;
-
-  LocalMsrRegister = 0;
-  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
-  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
-  ((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 0;
-  ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
-  ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 1;
-
-  TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
-  TaskPtr.DataTransfer.DataSizeInDwords = 2;
-  TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
-  TaskPtr.DataTransfer.DataTransferFlags = 0;
-  TaskPtr.ExeFlags = WAIT_FOR_CORE;
-  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
-  return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable Software C1e on a family 10h core.
- *
- * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
- * @param[in]    StdHeader          Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeSwC1eOnCore (
-  IN       VOID *IntPendMsr,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT64  LocalMsrRegister;
-
-  // Enable C1e
-  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
-
-  // Set OS Visible Workaround Status BIT1 to indicate that C1e
-  // is enabled.
-  LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
-  LocalMsrRegister |= BIT1;
-  LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
-}
-
-
-CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e =
-{
-  0,
-  F10IsSwC1eSupported,
-  F10InitializeSwC1e
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
deleted file mode 100644
index 407db95..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 revision Cx specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h rev C.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 48937 $   @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set down core register on a revision C processor.
- *
- * This function set F3x190 Downcore Control Register[5:0]
- *
- * @param[in]   FamilySpecificServices   The current Family Specific Services.
- * @param[in]   Socket                   Socket ID.
- * @param[in]   Module                   Module ID in socket.
- * @param[in]   LeveledCores             Number of core.
- * @param[in]   CoreLevelMode            Core level mode.
- * @param[in]   StdHeader                Header for library and services.
- *
- * @retval      TRUE                     Down Core register is updated.
- * @retval      FALSE                    Down Core register is not updated.
- */
-BOOLEAN
-F10CommonRevCSetDownCoreRegister (
-  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
-  IN       UINT32 *Socket,
-  IN       UINT32 *Module,
-  IN       UINT32 *LeveledCores,
-  IN       CORE_LEVELING_TYPE CoreLevelMode,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32    TempVar32_a;
-  UINT32    CoreDisableBits;
-  PCI_ADDR  PciAddress;
-  BOOLEAN   IsUpdated;
-  AGESA_STATUS AgesaStatus;
-
-  IsUpdated = FALSE;
-
-  switch (*LeveledCores) {
-  case 1:
-    CoreDisableBits = DOWNCORE_MASK_SINGLE;
-    break;
-  case 2:
-    CoreDisableBits = DOWNCORE_MASK_DUAL;
-    break;
-  case 3:
-    CoreDisableBits = DOWNCORE_MASK_TRI;
-    break;
-  default:
-    CoreDisableBits = 0;
-    break;
-  }
-
-  if (CoreDisableBits != 0) {
-    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
-
-      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
-      TempVar32_a = (TempVar32_a >> 12) & 0x3;
-      if (TempVar32_a == 0) {
-        CoreDisableBits &= 0x1;
-      } else if (TempVar32_a == 1) {
-        CoreDisableBits &= 0x3;
-      } else if (TempVar32_a == 2) {
-        CoreDisableBits &= 0x7;
-      } else if (TempVar32_a == 3) {
-        CoreDisableBits &= 0x0F;
-      }
-      PciAddress.Address.Register = DOWNCORE_CTRL;
-      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
-      if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
-        TempVar32_a |= CoreDisableBits;
-        LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
-        IsUpdated = TRUE;
-      }
-    }
-  }
-
-  return IsUpdated;
-}
-
-
-CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
-{
-  0,
-  F10CommonRevCSetDownCoreRegister
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Get CPU pstate current on a revision C processor.
- *
- *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- *    This function returns the ProcIddMax.
- *
- *  @param[in]     FamilySpecificServices    The current Family Specific Services.
- *  @param[in]     Pstate                    The P-state to check.
- *  @param[out]    ProcIddMax                P-state current in mA.
- *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
- *
- *  @retval        TRUE                      P-state is enabled
- *  @retval        FALSE                     P-state is disabled
- */
-BOOLEAN
-F10CommonRevCGetProcIddMax (
-  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
-  IN       UINT8                  Pstate,
-     OUT   UINT32                 *ProcIddMax,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  )
-{
-  UINT32       IddDiv;
-  UINT32       CmpCap;
-  UINT32       LocalPciRegister;
-  UINT32       Socket;
-  UINT32       Module;
-  UINT32       Ignored;
-  UINT32       MsrAddress;
-  UINT32       SinglePlaneNbIdd;
-  UINT64       PstateMsr;
-  BOOLEAN      IsPstateEnabled;
-  PCI_ADDR     PciAddress;
-  AGESA_STATUS IgnoredSts;
-
-  IsPstateEnabled = FALSE;
-
-  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
-
-  ASSERT (MsrAddress <= PS_MAX_REG);
-
-  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
-  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
-    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
-    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
-    PciAddress.Address.Function = FUNC_3;
-    PciAddress.Address.Register = NB_CAPS_REG;
-    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
-    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
-    CmpCap++;
-
-    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
-    case 0:
-      IddDiv = 1000;
-      break;
-    case 1:
-      IddDiv = 100;
-      break;
-    case 2:
-      IddDiv = 10;
-      break;
-    default:  // IddDiv = 3 is reserved. Use 10
-      ASSERT (FALSE);
-      IddDiv = 10;
-      break;
-    }
-
-    PciAddress.Address.Register = PW_CTL_MISC_REG;
-    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
-    if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) {
-      *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
-    } else {
-      PciAddress.Address.Register = PRCT_INFO_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
-      SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->SinglePlaneNbIdd;
-      SinglePlaneNbIdd <<= 1;
-      *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
-    }
-    IsPstateEnabled = TRUE;
-  }
-  return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[in]   PciAddress               The northbridge to query by pci base address.
- *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
- *  @param[in]   StdHeader                Header for library and services
- *
- *  @retval      TRUE                    Perform northbridge frequency and voltage config.
- *  @retval      FALSE                   Do not configure them.
- */
-BOOLEAN
-F10CommonRevCGetNbCofVidUpdate (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-  IN       PCI_ADDR *PciAddress,
-     OUT   BOOLEAN *NbVidUpdateAll,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32 ProductInfoRegister;
-
-  PciAddress->Address.Register = PRCT_INFO_REG;
-  PciAddress->Address.Function = FUNC_3;
-  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
-  *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
-  return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Determines the NB clock on the desired node.
- *
- *  @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- *  @param[in]     FamilySpecificServices  The current Family Specific Services.
- *  @param[in]     PlatformConfig          Platform profile/build option config structure.
- *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
- *  @param[in]     NbPstate                The NB P-state number to check.
- *  @param[out]    FreqNumeratorInMHz      The desired node's frequency numerator in megahertz.
- *  @param[out]    FreqDivisor             The desired node's frequency divisor.
- *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- *  @retval        TRUE                    NbPstate is valid
- *  @retval        FALSE                   NbPstate is disabled or invalid
- */
-BOOLEAN
-F10CommonRevCGetNbPstateInfo (
-  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       PCI_ADDR               *PciAddress,
-  IN       UINT32                 NbPstate,
-     OUT   UINT32                 *FreqNumeratorInMHz,
-     OUT   UINT32                 *FreqDivisor,
-     OUT   UINT32                 *VoltageInuV,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  )
-{
-  UINT32   NbFid;
-  UINT32   NbVid;
-  UINT32   LocalPciRegister;
-  UINT32   ProductInfoRegister;
-  UINT64   LocalMsrRegister;
-  BOOLEAN  PstateIsValid;
-
-  PstateIsValid = TRUE;
-  if (NbPstate == 0) {
-    *FreqDivisor = 1;
-  } else if ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
-    *FreqDivisor = 2;
-  } else {
-    PstateIsValid = FALSE;
-  }
-  if (PstateIsValid) {
-    PciAddress->Address.Function = FUNC_3;
-    PciAddress->Address.Register = PRCT_INFO_REG;
-    LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
-    if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
-      PciAddress->Address.Register = CPTC0_REG;
-      LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
-      NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
-      LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
-      NbVid = (UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid;
-    } else {
-      NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
-      NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
-      PciAddress->Address.Register = PW_CTL_MISC_REG;
-      LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
-      if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
-        NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
-        NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
-      }
-    }
-    *FreqNumeratorInMHz = ((NbFid + 4) * 200);
-    *VoltageInuV = (1550000 - (12500 * NbVid));
-  }
-  return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns the node's minimum and maximum northbridge frequency.
- *
- *  @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
- *
- *  @param[in]     FamilySpecificServices  The current Family Specific Services.
- *  @param[in]     PlatformConfig          Platform profile/build option config structure.
- *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
- *  @param[out]    MinFreqInMHz            The node's miminum northbridge frequency.
- *  @param[out]    MaxFreqInMHz            The node's maximum northbridge frequency.
- *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
- *
- *  @retval        AGESA_STATUS            Northbridge frequency is valid
- */
-AGESA_STATUS
-F10RevCGetMinMaxNbFrequency (
-  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       PCI_ADDR               *PciAddress,
-     OUT   UINT32                 *MinFreqInMHz,
-     OUT   UINT32                 *MaxFreqInMHz,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  )
-{
-  UINT32         NbPstateEn;
-  UINT32         NbFid;
-  UINT32         FreqDivisor;
-  UINT32         FreqNumerator;
-  UINT32         LocalPciRegister;
-  UINT32         ProductInfoRegister;
-  CPU_LOGICAL_ID LogicalId;
-
-  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-
-  FreqDivisor = 1;
-
-  // If NB P-state is supported, return the frequency of NB P-state 1
-  if ((PlatformConfig->PlatformProfile.PlatformPowerPolicy != Performance) &&
-     ((LogicalId.Revision & AMD_F10_C3) != 0)) {
-    PciAddress->Address.Function = FUNC_3;
-    PciAddress->Address.Register = 0x1F0;
-    LibAmdPciReadBits (*PciAddress, 18, 16, &NbPstateEn, StdHeader);
-
-    if (NbPstateEn != 0) {
-      FreqDivisor = 2;
-    }
-  }
-
-  PciAddress->Address.Function = FUNC_3;
-  PciAddress->Address.Register = PRCT_INFO_REG;
-  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
-
-  if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
-    PciAddress->Address.Register = CPTC0_REG;
-    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
-    NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
-  } else {
-    NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
-    PciAddress->Address.Register = PW_CTL_MISC_REG;
-    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
-    if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
-      NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
-    }
-  }
-
-  FreqNumerator = ((NbFid + 4) * 200);
-  *MaxFreqInMHz = FreqNumerator;
-  *MinFreqInMHz = (FreqNumerator / FreqDivisor);
-
-  return AGESA_SUCCESS;
-
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is the Northbridge PState feature enabled?
- *
- * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
- *
- * @param[in]      FamilySpecificServices         The current Family Specific Services.
- * @param[in]      PlatformConfig                 Platform profile/build option config structure.
- * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
- *
- * @retval         TRUE                           The NB PState feature is enabled.
- * @retval         FALSE                          The NB PState feature is not enabled.
- */
-BOOLEAN
-F10CommonRevCIsNbPstateEnabled (
-  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  )
-{
-  UINT32         Core;
-  UINT32         Module;
-  UINT32         NbPstate;
-  UINT32         Socket;
-  PCI_ADDR       PciAddress;
-  AGESA_STATUS   IgnoredSts;
-  CPU_LOGICAL_ID LogicalId;
-  BOOLEAN        Result;
-
-  Result = FALSE;
-
-  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-  if (((LogicalId.Revision & AMD_F10_C3) != 0) && (!IsNonCoherentHt1 (StdHeader))) {
-    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-    PciAddress.Address.Function = FUNC_3;
-    PciAddress.Address.Register = 0x1F0;
-    LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
-    if (NbPstate != 0) {
-      Result = TRUE;
-    }
-  }
-  return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the number of physical cores of current processor.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
- *
- * @param[in]      FamilySpecificServices         The current Family Specific Services.
- * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
- *
- * @return         The number of physical cores.
- */
-UINT8
-F10CommonRevCGetNumberOfPhysicalCores (
-  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  )
-{
-  UINT32       Socket;
-  UINT32       Module;
-  UINT32       Core;
-  UINT32       LocalPciRegister;
-  PCI_ADDR     PciAddress;
-  AGESA_STATUS IgnoredSts;
-
-  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-  PciAddress.Address.Function = FUNC_3;
-  PciAddress.Address.Register = NB_CAPS_REG;
-  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-  return (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo + 1);
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
deleted file mode 100644
index a254928..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
-{
-  0x1040, 0x1040,
-  0x1041, 0x1041,
-  0x1042, 0x1041,
-  0x1043, 0x1043
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns the appropriate microcode patch equivalent ID table.
- *
- *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[out]  RbEquivalenceTablePtr    Points to the first entry in the table.
- *  @param[out]  NumberOfElements         Number of valid entries in the table.
- *  @param[in]   StdHeader                Header for library and services.
- *
- */
-VOID
-GetF10RbMicrocodeEquivalenceTable (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-     OUT   CONST VOID **RbEquivalenceTablePtr,
-     OUT   UINT8 *NumberOfElements,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
-  *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
deleted file mode 100644
index bf98025..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  HT   Phy   T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] =
-{
-// Erratum 354
-// 0x40:0x48
-  {
-    HtPhyRangeRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      (AMD_F10_RB_C1)                     // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL0_HT3,               //
-      0x40, 0x48,                           // Address
-      0x00000040,                           // regData
-      0x00000040,                           // regMask
-    }}
-  },
-// 0x50:0x58
-  {
-    HtPhyRangeRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      (AMD_F10_RB_C1)                     // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      HTPHY_LINKTYPE_SL1_HT3,               //
-      0x50, 0x58,                           // Address
-      0x00000040,                           // regData
-      0x00000040,                           // regMask
-    }}
-  },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10RbHtPhyRegisters
-};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
deleted file mode 100644
index ad356b1..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] =
-{
-  {
-    0x1040,
-    AMD_F10_RB_C0
-  },
-  {
-    0x1041,
-    AMD_F10_RB_C1
-  },
-  {
-    0x1042,
-    AMD_F10_RB_C2
-  },
-  {
-    0x1043,
-    AMD_F10_RB_C3
-  }
-};
-
-VOID
-GetF10RbLogicalIdAndRev (
-     OUT   CONST CPU_LOGICAL_ID_XLAT **RbIdPtr,
-     OUT   UINT8 *NumberOfElements,
-     OUT   UINT64 *LogicalFamily,
-  IN OUT   AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
-  *RbIdPtr = CpuF10RbLogicalIdAndRevArray;
-  *LogicalFamily = AMD_FAMILY_10_RB;
-}
-
-//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev =
-//{
-//  (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
-//  (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray
-//};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
deleted file mode 100644
index ab45bda..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB microcode patches
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/Family/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Returns a table containing the appropriate microcode patches.
- *
- *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- *  @param[in]   FamilySpecificServices   The current Family Specific Services.
- *  @param[out]  RbUcodePtr               Points to the first entry in the table.
- *  @param[out]  NumberOfElements         Number of valid entries in the table.
- *  @param[in]   StdHeader                Header for library and services.
- *
- */
-VOID
-GetF10RbMicroCodePatchesStruct (
-  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
-     OUT   CONST VOID **RbUcodePtr,
-     OUT   UINT8 *NumberOfElements,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  *NumberOfElements = CpuF10RbNumberOfMicrocodePatches;
-  *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
deleted file mode 100644
index 6d2dc23..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] =
-{
-//  M S R    T a b l e s
-// ----------------------
-
-// MSR_DC_CFG (0xC0011022)
-// bits[43:42] = 0
-// Errata #326
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                       // CpuFamily
-      AMD_F10_RB_C0                        // CpuRevision
-    },
-    {AMD_PF_MULTI_LINK},                     // platformFeatures
-    {{
-      MSR_DC_CFG,                            // MSR Address
-      0x0000000000000000,                    // OR Mask
-      0x00000C0000000000,                    // NAND Mask
-    }}
-  },
-
-// MSR_BU_CFG (0xC0011023)
-// Erratum #309 BU_CFG[23]=1
-  {
-    MsrRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_RB_C0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                            // platformFeatures
-    {{
-      MSR_BU_CFG,                            // MSR Address
-      (1 << 23),                             // OR Mask
-      (1 << 23),                             // NAND Mask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = {
-  AllCores,
-  (sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  (TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
deleted file mode 100644
index f4801b9..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//  P C I    T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] =
-{
-  // Function 0
-
-// F0x16C - Link Global Extended Control Register, Errata 351
-// bit[15:13] ForceFullT0 = 0
-// bit[5:0] T0Time = 0x14
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x00000014,                           // regData
-      0x0000E03F,                           // regMask
-    }}
-  },
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_RB_C3                       // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x00000040,                           // regData
-      0x000000C0,                           // regMask
-    }}
-  },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_RB_C3                      // CpuRevision
-    },
-    {AMD_PF_SINGLE_LINK},                   // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
-      0x0000C226,                           // regData
-      0x0000E23F,                           // regMask
-    }}
-  },
-// F0x170 - Link Extended Control Register - Link 0, sublink 0
-// Errata 351 (only need to override single link case.)
-// bit[8] LS2En = 0,
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-     (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
-      0x00000000,                           // regData
-      0x00000100,                           // regMask
-    }}
-  },
-
-
-// F3xA0 - Power Control Miscellaneous
-// bits[13:11] PllLockTime = 5
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_RB_C0                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
-      0x00002800,                           // regData
-      0x00003800,                           // regMask
-    }}
-  },
-// F3xA0 - Power Control Miscellaneous
-// bits[28] NbPstateForce = 1
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_RB_C3                       // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
-      0x10000000,                           // regData
-      0x10000000,                           // regMask
-    }}
-  },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 6
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_RB_ALL                      // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
-      0x00006000,                           // regData
-      0x00007000,                           // regMask
-    }}
-  },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
-  {
-    PciRegister,
-    {
-      AMD_FAMILY_10,                      // CpuFamily
-      AMD_F10_C0                          // CpuRevision
-    },
-    {AMD_PF_ALL},                           // platformFeatures
-    {{
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
-      0x00005000,                           // regData
-      0x00007000,                           // regMask
-    }}
-  },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
-  {
-    ProfileFixup,
-    {
-      AMD_FAMILY_10,                        // CpuFamily
-      AMD_F10_C3                            // CpuRevision
-    },
-    {AMD_PF_ALL},                             // platformFeatures
-    {{
-      PERFORMANCE_NB_PSTATES_ENABLE,        // PerformanceFeatures
-      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
-      0x00005000,                           // regData
-      0x00007000,                           // regMask
-    }}
-  }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
-  PrimaryCores,
-  (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
-  F10RbPciRegisters,
-};
-
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
deleted file mode 100644
index 6080214..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c4 for 1081 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/REVD
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c4 for 1081 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4 =
-{{
-0x10,
-0x20,
-0x03,
-0x03,
-0xc4,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x01,
-0x4a,
-0xe0,
-0x9c,
-0x93,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x81,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0xa7,
-0x0b,
-0x00,
-0x00,
-0x14,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x4f,
-0xdf,
-0x38,
-0x00,
-0x81,
-0x3f,
-0x20,
-0xc0,
-0x4e,
-0xf0,
-0xff,
-0xbf,
-0x0f,
-0xff,
-0x5e,
-0x3f,
-0xf0,
-0xdf,
-0xad,
-0x07,
-0x3d,
-0xf8,
-0x7b,
-0x7b,
-0xc0,
-0x00,
-0xd4,
-0x00,
-0x13,
-0xf1,
-0xff,
-0xff,
-0xac,
-0xe1,
-0x1f,
-0xe0,
-0x4e,
-0xfe,
-0xbb,
-0xff,
-0xfe,
-0x87,
-0x7f,
-0xa7,
-0x03,
-0xf8,
-0x7f,
-0xd6,
-0x7c,
-0x1e,
-0xfa,
-0xbd,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x00,
-0x3d,
-0x57,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x2e,
-0xfe,
-0xff,
-0xc0,
-0xcf,
-0xc3,
-0x3f,
-0xeb,
-0x01,
-0xfc,
-0x77,
-0x5a,
-0x3e,
-0x0f,
-0xfd,
-0x35,
-0x00,
-0x90,
-0x3e,
-0xff,
-0x9f,
-0xe0,
-0xfd,
-0x65,
-0x60,
-0x75,
-0xf8,
-0x9f,
-0xff,
-0x97,
-0xff,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xf5,
-0xde,
-0xff,
-0x7e,
-0x2c,
-0x9f,
-0x87,
-0xff,
-0x1e,
-0x00,
-0xf8,
-0x6f,
-0x95,
-0x03,
-0x50,
-0xf4,
-0x03,
-0xf8,
-0x1c,
-0xf8,
-0xff,
-0x3f,
-0x00,
-0xf0,
-0xee,
-0x84,
-0xfc,
-0xfe,
-0xff,
-0xff,
-0x22,
-0xc3,
-0x1f,
-0x51,
-0x96,
-0x38,
-0x16,
-0x0d,
-0x00,
-0xf8,
-0xfe,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe5,
-0xa6,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfa,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x3f,
-0xe3,
-0x3e,
-0x0f,
-0xfd,
-0x50,
-0x03,
-0xb0,
-0xdf,
-0x8c,
-0xf9,
-0x3c,
-0xf4,
-0x43,
-0x0e,
-0xc0,
-0xfd,
-0x32,
-0xe5,
-0xf3,
-0xd0,
-0x0f,
-0x03,
-0x00,
-0x03,
-0x25,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xff,
-0xff,
-0x00,
-0xfd,
-0xbb,
-0x14,
-0xf2,
-0xc3,
-0x2f,
-0xf8,
-0x13,
-0xcc,
-0x7f,
-0x0c,
-0xb8,
-0x0e,
-0x74,
-0xf5,
-0x03,
-0xf0,
-0xf8,
-0x33,
-0x03,
-0x1c,
-0x2b,
-0xd7,
-0x00,
-0x00,
-0xeb,
-0xe5,
-0x1f,
-0x80,
-0xc0,
-0x1f,
-0x1b,
-0xe0,
-0x9e,
-0x9b,
-0x7f,
-0x00,
-0x03,
-0x7f,
-0x6c,
-0x80,
-0xf8,
-0x7d,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0x80,
-0xd7,
-0x62,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x38,
-0x00,
-0x43,
-0xdf,
-0xa0,
-0xd7,
-0x83,
-0x3f,
-0xe3,
-0x00,
-0x3c,
-0x75,
-0x80,
-0x5e,
-0x07,
-0xfe,
-0xff,
-0xef,
-0x7a,
-0xc1,
-0x73,
-0xfd,
-0x3c,
-0xfc,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xff,
-0xff,
-0x17,
-0xff,
-0xdf,
-0xeb,
-0xff,
-0xe1,
-0xb7,
-0xf5,
-0x00,
-0xfe,
-0x7f,
-0x6e,
-0x80,
-0x07,
-0xff,
-0xff,
-0x6f,
-0x11,
-0xfe,
-0xb5,
-0xaa,
-0x1f,
-0xff,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xff,
-0x7f,
-0x8b,
-0xf0,
-0xaf,
-0x75,
-0xff,
-0xff,
-0xdb,
-0x7f,
-0x2f,
-0xc3,
-0xbf,
-0x57,
-0xf5,
-0x0c,
-0xf1,
-0xff,
-0xb7,
-0x0f,
-0xff,
-0x00,
-0x3f,
-0x70,
-0xa2,
-0x35,
-0x00,
-0xe0,
-0xff,
-0x1b,
-0x0f,
-0x79,
-0xe8,
-0xd7,
-0xf2,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x2f,
-0x3a,
-0xc1,
-0xff,
-0xfd,
-0x3c,
-0xfc,
-0x6b,
-0x1e,
-0xc0,
-0x7f,
-0xb6,
-0x0c,
-0xf0,
-0xe0,
-0x4f,
-0xff,
-0x2f,
-0x43,
-0xfc,
-0xc0,
-0xcf,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xff,
-0x67,
-0x81,
-0xff,
-0xb1,
-0xee,
-0x1f,
-0xfe,
-0x1b,
-0x0f,
-0xe0,
-0xff,
-0xf7,
-0xf6,
-0x7a,
-0xf0,
-0xef,
-0xbf,
-0x96,
-0xff,
-0x1d,
-0xab,
-0xfe,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x6f,
-0xff,
-0xb1,
-0xfc,
-0x7f,
-0x58,
-0x59,
-0x0e,
-0xc0,
-0xff,
-0x2f,
-0x72,
-0xfc,
-0x03,
-0xfc,
-0x3c,
-0x7f,
-0x31,
-0x1e,
-0xc0,
-0xe0,
-0x4f,
-0xec,
-0x75,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xd7,
-0xf8,
-0xff,
-0x45,
-0x87,
-0x7f,
-0xa2,
-0x9f,
-0x19,
-0xff,
-0xff,
-0x67,
-0x1f,
-0xfe,
-0xb1,
-0xae,
-0x65,
-0xfc,
-0xff,
-0xff,
-0x7e,
-0xf8,
-0xf7,
-0xba,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0xdb,
-0x7a,
-0xc0,
-0x83,
-0x3f,
-0x31,
-0x01,
-0xfc,
-0x67,
-0xff,
-0xf4,
-0x0f,
-0xdf,
-0x5a,
-0x4f,
-0xf0,
-0xff,
-0xff,
-0xd8,
-0x3a,
-0xfc,
-0x32,
-0x00,
-0xc0,
-0x01,
-0x48,
-0x7f,
-0x97,
-0xf1,
-0xff,
-0xe0,
-0xac,
-0xe1,
-0x1f,
-0xff,
-0x5a,
-0xfe,
-0xbb,
-0xad,
-0xff,
-0x87,
-0x7f,
-0xfe,
-0x03,
-0xf8,
-0xff,
-0xb5,
-0xe8,
-0x1f,
-0xbe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x5f,
-0xcb,
-0x7f,
-0xab,
-0x75,
-0xe5,
-0xf0,
-0xdb,
-0x7a,
-0x00,
-0xff,
-0x3f,
-0x91,
-0xcf,
-0x43,
-0x0f,
-0xf8,
-0x13,
-0x90,
-0xbf,
-0x0c,
-0xb6,
-0x0e,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x7f,
-0x5b,
-0x0f,
-0xe0,
-0xf0,
-0x27,
-0x06,
-0x78,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x5b,
-0x8b,
-0xfe,
-0xca,
-0x07,
-0xfc,
-0x09,
-0x87,
-0x5f,
-0x06,
-0x5b,
-0x20,
-0x00,
-0x09,
-0x00,
-0xb0,
-0xc0,
-0x8d,
-0x03,
-0x3c,
-0xf8,
-0x03,
-0x02,
-0x80,
-0xf8,
-0xff,
-0x3f,
-0xfc,
-0xf0,
-0xce,
-0x85,
-0x04,
-0x3a,
-0x0e,
-0xfe,
-0xae,
-0xc3,
-0x1f,
-0x03,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x77,
-0x01,
-0x00,
-0xf8,
-0xee,
-0x1f,
-0xfe,
-0xb9,
-0x3f,
-0x65,
-0x40,
-0xe0,
-0xf8,
-0x79,
-0xf8,
-0x07,
-0xff,
-0x94,
-0xf3,
-0xff,
-0xea,
-0xfa,
-0xe0,
-0x5f,
-0x06,
-0x00,
-0x7a,
-0xbc,
-0xff,
-0xa5,
-0xfe,
-0x77,
-0x52,
-0x3f,
-0x0f,
-0xff,
-0xff,
-0xef,
-0xf2,
-0xfe,
-0x03,
-0xfc,
-0x3c,
-0xfc,
-0x77,
-0x1f,
-0xe0,
-0x7f,
-0x2f,
-0xe5,
-0xf3,
-0xd0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
deleted file mode 100644
index c2317a4..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c5 for 1080 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/FAMILY/0x10/REVD
- * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c5 for 1080 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5 =
-{{
-0x10,
-0x20,
-0x05,
-0x03,
-0xc5,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x83,
-0xc5,
-0x93,
-0xcd,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x80,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x89,
-0x0b,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xf8,
-0xff,
-0x2e,
-0xc3,
-0x3f,
-0xd7,
-0xfd,
-0xac,
-0xff,
-0xff,
-0xbb,
-0x0f,
-0xff,
-0x5c,
-0xd7,
-0xf3,
-0xdf,
-0xfd,
-0xc7,
-0x3f,
-0xfc,
-0xe3,
-0xf5,
-0x00,
-0x1d,
-0xd5,
-0x00,
-0x00,
-0xfd,
-0xff,
-0x7f,
-0xfa,
-0xe1,
-0xd9,
-0xca,
-0x00,
-0x66,
-0xfa,
-0x71,
-0x80,
-0x07,
-0x7f,
-0x40,
-0x67,
-0xd9,
-0xff,
-0xff,
-0xde,
-0x1d,
-0x7e,
-0xb1,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x10,
-0x59,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0x0c,
-0x94,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0x30,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0xac,
-0x5c,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x80,
-0x5f,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
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-}};
-
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
deleted file mode 100644
index df2f9ec..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RevD L3 dependent feature support functions.
- *
- * Provides the functions necessary to initialize L3 dependent feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 49216 $   @e \$Date: 2011-03-19 11:34:39 +0800 (Sat, 19 Mar 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-
-/*
- *----------------------------------------------------------------------------
- *                                MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "CommonReturns.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuLateInit.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuL3Features.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE
-/*----------------------------------------------------------------------------
- *                          DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                           TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * The family 10h background scrubber context structure.
- *
- * These fields need to be saved, modified, then restored
- * per die as part of HT Assist initialization.
- */
-typedef struct {
-  UINT32  DramScrub:5;               ///< DRAM scrub rate
-  UINT32  :3;                        ///< Reserved
-  UINT32  L3Scrub:5;                 ///< L3 scrub rate
-  UINT32  :3;                        ///< Reserved
-  UINT32  Redirect:1;                ///< DRAM scrubber redirect enable
-  UINT32  :15;                       ///< Reserved
-} F10_SCRUB_CONTEXT;
-
-
-/*----------------------------------------------------------------------------
- *                        PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- *                            EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern
-VOID
-F10RevDProbeFilterCritical (
-  IN       PCI_ADDR PciAddress,
-  IN       UINT32   LocalPciRegister
-  );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Check to see if the input CPU supports L3 dependent features.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    Socket              Processor socket to check.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- * @retval       TRUE                L3 dependent features are supported.
- * @retval       FALSE               L3 dependent features are not supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsL3FeatureSupported (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       UINT32 Socket,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32       Module;
-  UINT32       LocalPciRegister;
-  BOOLEAN      IsSupported;
-  PCI_ADDR     PciAddress;
-  AGESA_STATUS IgnoredStatus;
-
-  IsSupported = FALSE;
-  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
-    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = NB_CAPS_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) {
-        IsSupported = TRUE;
-      }
-      break;
-    }
-  }
-  return IsSupported;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Check to see if the input CPU supports HT Assist.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- * @retval       TRUE                HT Assist is supported.
- * @retval       FALSE               HT Assist cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-F10IsHtAssistSupported (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       PLATFORM_CONFIGURATION *PlatformConfig,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  BOOLEAN          IsSupported;
-  UINT32           CpuCount;
-  AP_MAILBOXES     ApMailboxes;
-
-  IsSupported = FALSE;
-
-  if (PlatformConfig->PlatformProfile.UseHtAssist) {
-    CpuCount = GetNumberOfProcessors (StdHeader);
-    ASSERT (CpuCount != 0);
-
-    if (CpuCount == 1) {
-      GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
-      if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
-        IsSupported = TRUE;
-      }
-    } else if (CpuCount > 1) {
-      IsSupported = TRUE;
-    }
-  }
-  return IsSupported;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Enable the Probe filter feature.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    Socket              Processor socket to check.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10HtAssistInit (
-  IN       L3_FEATURE_FAMILY_SERVICES  *L3FeatureServices,
-  IN       UINT32  Socket,
-  IN       AMD_CONFIG_PARAMS      *StdHeader
-  )
-{
-  UINT32                     Module;
-  UINT32                     LocalPciRegister;
-  PCI_ADDR                   PciAddress;
-  AGESA_STATUS               IgnoredStatus;
-
-  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
-    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = L3_CACHE_PARAM_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit = 1;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      do {
-        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      } while (((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit != 0);
-
-      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFMode = 0;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-
-      F10RevDProbeFilterCritical (PciAddress, LocalPciRegister);
-
-      do {
-        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      } while (((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFInitDone != 1);
-      IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
-    }
-  }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Save the current settings of the scrubbers, and disabled them.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    Socket              Processor socket to check.
- * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10GetL3ScrubCtrl (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       UINT32 Socket,
-  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32       Module;
-  UINT32       ScrubCtrl;
-  UINT32       ScrubAddr;
-  PCI_ADDR     PciAddress;
-  AGESA_STATUS IgnoredStatus;
-
-  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
-    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-
-      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
-
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
-
-      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
-
-      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
-        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
-      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
-        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
-      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
-        ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
-
-      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
-      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
-      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
-      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
-    }
-  }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Restore the initial settings for the scrubbers.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    Socket              Processor socket to check.
- * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10SetL3ScrubCtrl (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       UINT32 Socket,
-  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32       Module;
-  UINT32       LocalPciRegister;
-  PCI_ADDR     PciAddress;
-  AGESA_STATUS IgnoredStatus;
-
-  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
-    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-
-      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
-
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub =
-        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
-      ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub =
-        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-
-      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn =
-        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-    }
-  }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Set MSR bits required for L3 dependent features on each core.
- *
- * @param[in]    L3FeatureServices   L3 feature family services.
- * @param[in]    HtAssistEnabled     Indicates whether Ht Assist is enabled.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10HookDisableCache (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       BOOLEAN HtAssistEnabled,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT64  LocalMsrRegister;
-
-  LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
-  LocalMsrRegister |= BIT42;
-  LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Hook before L3 features initialization sequence.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    Socket              Processor socket to check.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10HookBeforeInit (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       UINT32 Socket,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  UINT32          Module;
-  UINT32          LocalPciRegister;
-  UINT32          PfCtrlRegister;
-  PCI_ADDR        PciAddress;
-  CPU_LOGICAL_ID  LogicalId;
-  AGESA_STATUS    IgnoredStatus;
-  UINT32          PackageType;
-
-  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
-  PackageType = LibAmdGetPackageType (StdHeader);
-
-  LocalPciRegister = 0;
-  ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFWayNum = 2;
-  ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFSubCacheEn = 15;
-  ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFLoIndexHashEn = 1;
-  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
-    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-      PciAddress.Address.Function = FUNC_3;
-      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
-      LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
-      ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFPreferredSORepl =
-        ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
-      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-
-      // Assumption: all socket use the same CPU package.
-      if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
-        // Apply erratum #384
-        // Set F2x11C[13:12] = 11b
-        PciAddress.Address.Function = FUNC_2;
-        PciAddress.Address.Register = 0x11C;
-        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-        LocalPciRegister |= 0x3000;
-        LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      }
-    }
-  }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  Check to see if the input CPU is running in the optimal configuration.
- *
- * @param[in]    L3FeatureServices   L3 Feature family services.
- * @param[in]    Socket              Processor socket to check.
- * @param[in]    StdHeader           Config Handle for library, services.
- *
- * @retval       TRUE               HT Assist is running sub-optimally.
- * @retval       FALSE              HT Assist is running optimally.
- *
- */
-BOOLEAN
-F10IsNonOptimalConfig (
-  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
-  IN       UINT32 Socket,
-  IN       AMD_CONFIG_PARAMS *StdHeader
-  )
-{
-  BOOLEAN      IsNonOptimal;
-  BOOLEAN      IsMemoryPresent;
-  UINT32       Module;
-  UINT32       LocalPciRegister;
-  PCI_ADDR     PciAddress;
-  AGESA_STATUS IgnoredStatus;
-
-  IsNonOptimal = FALSE;
-  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
-    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-      IsMemoryPresent = FALSE;
-      PciAddress.Address.Function = FUNC_2;
-      PciAddress.Address.Register = DRAM_CFG_HI_REG0;
-
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
-        IsMemoryPresent = TRUE;
-        if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) {
-          IsNonOptimal = TRUE;
-          break;
-        }
-      }
-
-      PciAddress.Address.Register = DRAM_CFG_HI_REG1;
-
-      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
-      if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
-        IsMemoryPresent = TRUE;
-        if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) {
-          IsNonOptimal = TRUE;
-          break;
-        }
-      }
-      if (!IsMemoryPresent) {
-        IsNonOptimal = TRUE;
-        break;
-      }
-    }
-  }
-  return IsNonOptimal;
-}
-
-
-CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features =
-{
-  0,
-  F10IsL3FeatureSupported,
-  F10GetL3ScrubCtrl,
-  F10SetL3ScrubCtrl,
-  F10HookBeforeInit,
-  (PF_L3_FEATURE_AFTER_INIT) CommonVoid,
-  F10HookDisableCache,
-  (PF_L3_FEATURE_ENABLE_CACHE) CommonVoid,
-  F10IsHtAssistSupported,
-  F10HtAssistInit,
-  F10IsNonOptimalConfig,
-  (PF_ATM_MODE_IS_SUPPORTED) CommonReturnFalse,
-  (PF_ATM_MODE_INIT) CommonVoid
-};
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
deleted file mode 100644
index a52ff50..0000000
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RevD Message-Based C1e feature support functions.
- *
- * Provides the functions necessary to initialize the message-based C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  CPU/F10
- * @e \$Revision: 46507 $   @e \$Date: 2011-02-04 07:16:19 +0800 (Fri, 04 Feb 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its