chip soc/intel/skylake

	# FSP Configuration
	register "DspEnable" = "0"
	register "ScsEmmcHs400Enabled" = "0"

	register "serirq_mode" = "SERIRQ_CONTINUOUS"

	# Enable PCIE slot
	register "PcieRpEnable[5]" = "1"
	register "PcieRpClkReqSupport[5]" = "1"
	register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1
	# RP6, uses CLK SRC 1
	register "PcieRpClkSrcNumber[5]" = "1"

	register "PcieRpEnable[6]" = "1"
	register "PcieRpClkReqSupport[6]" = "1"
	register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2
	# RP7, uses CLK SRC 2
	register "PcieRpClkSrcNumber[6]" = "2"

	register "PcieRpEnable[7]" = "1"
	register "PcieRpClkReqSupport[7]" = "1"
	register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
	# RP8, uses CLK SRC 3
	register "PcieRpClkSrcNumber[7]" = "3"

	register "PcieRpEnable[8]" = "1"
	register "PcieRpClkReqSupport[8]" = "1"
	register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
	# RP9, uses CLK SRC 4
	register "PcieRpClkSrcNumber[8]" = "4"

	register "PcieRpEnable[13]" = "1"
	register "PcieRpClkReqSupport[13]" = "1"
	register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5
	# RP14, uses CLK SRC 5
	register "PcieRpClkSrcNumber[13]" = "5"

	register "PcieRpEnable[16]" = "1"
	register "PcieRpClkReqSupport[16]" = "1"
	register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7
	# RP17, uses CLK SRC 7
	register "PcieRpClkSrcNumber[16]" = "7"

	# USB related
	register "SsicPortEnable" = "1"


	register "SerialIoDevMode" = "{
		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
		[PchSerialIoIndexUart0] = PchSerialIoPci,
		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
	}"

	# PL2 override 60W
	register "power_limits_config" = "{
		.tdp_pl2_override = 60,
	}"

	device domain 0 on
		device ref south_xhci on
			register "usb2_ports" = "{
				[0] = USB2_PORT_MID(OC_SKIP),	/* OTG */
				[1] = USB2_PORT_MID(OC3),	/* Touch Pad */
				[2] = USB2_PORT_MID(OC_SKIP),	/* M.2 BT */
				[3] = USB2_PORT_MID(OC_SKIP),	/* Touch Panel */
				[4] = USB2_PORT_MID(OC_SKIP),	/* M.2 WWAN */
				[5] = USB2_PORT_MID(OC0),	/* Front Panel */
				[6] = USB2_PORT_MID(OC0),	/* Front Panel */
				[7] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
				[8] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
				[9] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
				[10] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
				[11] = USB2_PORT_MID(OC_SKIP),	/* Finger print sensor */
				[12] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
				[13] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
			}"

			register "usb3_ports" = "{
				[0] = USB3_PORT_DEFAULT(OC5),		/* OTG */
				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* M.2 WWAN */
				[2] = USB3_PORT_DEFAULT(OC3),		/* Flex */
				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* IVCAM */
				[4] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
				[5] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
				[6] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
				[7] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
				[8] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
				[9] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
			}"
		end
		device ref sa_thermal	off end
		device ref i2c2		off end
		device ref i2c3		off end
		device ref sata		on
			register "SataSalpSupport" = "1"
			register "SataPortsEnable" = "{
				[0] = 1,
				[1] = 1,
				[2] = 1,
				[3] = 1,
				[4] = 1,
				[5] = 1,
				[6] = 1,
				[7] = 1,
			}"
		end
		device ref i2c4		off end
		device ref emmc		off end
		device ref sdxc		off end
		device ref hda		on  end
		device ref gbe		on  end
	end
end