diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 0a070b2..0978bfb 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -151,7 +151,6 @@
 	wrmsr
 
 	post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
 	/* Enable caching for ram init code to run faster */
 	movl	$MTRRphysBase_MSR(2), %ecx
 	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -161,7 +160,6 @@
 	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
-#endif
 
 	post_code(0x28)
 	/* Enable cache. */
@@ -219,7 +217,6 @@
 	andl    $~1, %eax
 	wrmsr
 
-#if CONFIG_CACHE_MRC_BIN
 	/* Clear MTRR that was used to cache MRC */
 	xorl	%eax, %eax
 	xorl	%edx, %edx
@@ -227,7 +224,6 @@
 	wrmsr
 	movl	$MTRRphysMask_MSR(2), %ecx
 	wrmsr
-#endif
 
 	post_code(0x33)
 
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 2d469ff..a3f1c64 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -146,7 +146,6 @@
 	wrmsr
 
 	post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
 	/* Enable caching for ram init code to run faster */
 	movl	$MTRRphysBase_MSR(2), %ecx
 	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -156,7 +155,6 @@
 	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
-#endif
 
 	post_code(0x28)
 	/* Enable cache. */
@@ -211,7 +209,6 @@
 	andl    $~1, %eax
 	wrmsr
 
-#if CONFIG_CACHE_MRC_BIN
 	/* Clear MTRR that was used to cache MRC */
 	xorl	%eax, %eax
 	xorl	%edx, %edx
@@ -219,7 +216,6 @@
 	wrmsr
 	movl	$MTRRphysMask_MSR(2), %ecx
 	wrmsr
-#endif
 
 	post_code(0x33)
 
diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig
index 471e522..753cfb3 100644
--- a/src/cpu/intel/socket_rPGA988B/Kconfig
+++ b/src/cpu/intel/socket_rPGA988B/Kconfig
@@ -8,8 +8,4 @@
 	select MMX
 	select SSE
 
-config CACHE_MRC_BIN
-	bool
-	default n
-
 endif
diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
index 83d29e7..1d1f64f 100644
--- a/src/cpu/intel/socket_rPGA989/Kconfig
+++ b/src/cpu/intel/socket_rPGA989/Kconfig
@@ -8,8 +8,4 @@
 	select MMX
 	select SSE
 
-config CACHE_MRC_BIN
-	bool
-	default n
-
 endif
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 0a251b8a..37dbd2b 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -19,7 +19,6 @@
 
 config NORTHBRIDGE_INTEL_HASWELL
 	bool
-	select CACHE_MRC_BIN
 	select CPU_INTEL_HASWELL
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 4dede09..093224f 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -19,7 +19,6 @@
 
 config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	bool
-	select CACHE_MRC_BIN
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select CPU_INTEL_MODEL_206AX
@@ -27,7 +26,6 @@
 
 config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE
 	bool
-	select CACHE_MRC_BIN
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select CPU_INTEL_MODEL_206AX
@@ -36,7 +34,6 @@
 
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
-	select CACHE_MRC_BIN
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select CPU_INTEL_MODEL_306AX
@@ -44,7 +41,6 @@
 
 config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
 	bool
-	select CACHE_MRC_BIN
 	select MMCONF_SUPPORT
 	select MMCONF_SUPPORT_DEFAULT
 	select CPU_INTEL_MODEL_306AX
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 5853118..524366c 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -14,7 +14,6 @@
 	select VGA_ROM_RUN if !PAYLOAD_SEABIOS
 	select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS
 	select BACKUP_DEFAULT_SMM_REGION
-	select CACHE_MRC_BIN
 	select CACHE_MRC_SETTINGS
 	select MRC_SETTINGS_PROTECT
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 05d4889..3f1b12a 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -153,7 +153,6 @@
 	wrmsr
 
 	post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
 	/* Enable caching for ram init code to run faster */
 	movl	$MTRRphysBase_MSR(2), %ecx
 	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
@@ -163,7 +162,6 @@
 	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
 	movl	$CPU_PHYSMASK_HI, %edx
 	wrmsr
-#endif
 
 	post_code(0x28)
 	/* Enable cache. */
@@ -239,7 +237,6 @@
 	andl    $~1, %eax
 	wrmsr
 
-#if CONFIG_CACHE_MRC_BIN
 	/* Clear MTRR that was used to cache MRC */
 	xorl	%eax, %eax
 	xorl	%edx, %edx
@@ -247,7 +244,6 @@
 	wrmsr
 	movl	$MTRRphysMask_MSR(2), %ecx
 	wrmsr
-#endif
 
 	post_code(0x33)