intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its
definitions under different names.
Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index bbaad83..cee7c2a 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -247,9 +247,9 @@
enable_lapic();
/* Force PCIRST# */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
udelay(200 * 1000);
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc();
early_superio_config_w83627thg();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 30ebf44..93b24a0 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -210,9 +210,9 @@
enable_lapic();
/* Force PCIRST# */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
udelay(200 * 1000);
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc();
early_superio_config();
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 9de0cfb..bd89609 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -108,10 +108,6 @@
#define GLBIOTLBINV (1 << 1)
#define GLBCTXTINV (1 << 0)
-/* Device 0:1.0 PCI configuration space (PCI Express) */
-
-#define BCTRL1 0x3e /* 16bit */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index f9167df..ebff49c 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -546,13 +546,13 @@
*/
/* First we reset the secondary bus */
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
- reg16 |= (1 << 6); /* SRESET */
- pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
+ reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
/* Read back and clear reset bit. */
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
- reg16 &= ~(1 << 6); /* SRESET */
- pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */
+ pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
@@ -610,12 +610,11 @@
reg32 |= 1;
pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
-
- reg16 |= (1 << 6);
- pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
- reg16 &= ~(1 << 6);
- pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
+ reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
+ reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff;
@@ -663,9 +662,9 @@
pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32);
/* Set VGA enable bit in PCIe bridge */
- reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), BCTRL1);
- reg16 |= (1 << 3);
- pci_write_config16(PCI_DEV(0, 0x1, 0), BCTRL1, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL);
+ reg16 |= PCI_BRIDGE_CTL_VGA;
+ pci_write_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL, reg16);
}
/* Enable GPEs */
@@ -776,17 +775,17 @@
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
- reg16 |= (1 << 6);
- pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
+ reg16 |= PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
reg32 |= (1 << 8);
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
- reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
- reg16 &= ~(1 << 6);
- pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET;
+ pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16);
printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff;
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index ebcc8bc..d19748e 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -86,7 +86,6 @@
#define SBUSN1 0x19 /* 8bit */
#define SUBUSN1 0x1a /* 8bit */
#define SSTS1 0x1e /* 16bit */
-#define BCTRL1 0x3e /* 16bit */
#define PEG_CAP 0xa2 /* 16bit */
#define DSTS 0xaa /* 16bit */
#define SLOTCAP 0xb4 /* 32bit */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 93024f6..21c2a39 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -153,10 +153,6 @@
#define SKPAD 0xdc /* Scratchpad Data */
-/* Device 0:1.0 PCI configuration space (PCI Express) */
-
-#define BCTRL1 0x3e /* 16bit */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index f53ff17..882f886 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -84,7 +84,6 @@
/* Device 0:1.0 PCI configuration space (PCI Express) */
-#define BCTRL1 0x3e /* 16bit */
#define PEGSTS 0x214 /* 32bit */
/* Device 0:2.0 PCI configuration space (Graphics Device) */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index b598c9b..d505728 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -101,10 +101,6 @@
#define SKPAD 0xdc /* Scratchpad Data */
-/* Device 0:1.0 PCI configuration space (PCI Express) */
-
-#define BCTRL1 0x3e /* 16bit */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index bdaced2..3652341 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -604,10 +604,10 @@
/* Set Cache Line Size to 0x10 */
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 94fa631..c8ca4f4 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -38,7 +38,8 @@
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE);
/* disable parity error response, enable ISA */
- pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2);
+ pci_update_config16(dev, PCI_BRIDGE_CONTROL,
+ ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
if (CONFIG(PCIE_DEBUG_INFO)) {
printk(BIOS_SPEW, " MBL = 0x%08x\n",
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index cb0691f..22b9107 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -101,10 +101,6 @@
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index a222893..833512a 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "pch.h"
@@ -36,10 +37,10 @@
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 &= ~PCI_BRIDGE_CTL_SERR;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 686930d..739f6ce 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -232,11 +233,10 @@
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 7fc0114..d615b40 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -59,10 +59,6 @@
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
#define ICH_PCIE_DEV_SLOT 28
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 4d98e89..d493b79 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
@@ -35,10 +36,10 @@
pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
- reg16 = pci_read_config16(dev, BCTRL);
- reg16 &= ~(1 << 0);
- reg16 &= ~(1 << 1);
- pci_write_config16(dev, BCTRL, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 &= ~PCI_BRIDGE_CTL_SERR;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 0946a9a..0d8b474 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "chip.h"
@@ -67,11 +68,10 @@
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 3b90ce6..b1d0ecc 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -41,10 +42,10 @@
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index 84b2b6a..64da5a7 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
@@ -41,10 +42,10 @@
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index e7cc9d2..f7b2929 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -82,10 +82,6 @@
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 3f37887..be4285b 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -195,10 +195,6 @@
#define SMLT 0x1b
#define SECSTS 0x1e
#define INTR 0x3c
-#define BCTRL 0x3e
-#define SBR (1 << 6)
-#define SEE (1 << 1)
-#define PERE (1 << 0)
/* Power Management Control and Status */
#define PCH_PCS 0x84
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index a3b2e09..1eb8e4b 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@@ -684,11 +685,10 @@
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
- reg16 = pci_read_config16(dev, 0x3e);
- reg16 &= ~(1 << 0); /* disable parity error response */
- // reg16 &= ~(1 << 1); /* disable SERR */
- reg16 |= (1 << 2); /* ISA enable */
- pci_write_config16(dev, 0x3e, reg16);
+ reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ reg16 &= ~PCI_BRIDGE_CTL_PARITY;
+ reg16 |= PCI_BRIDGE_CTL_NO_ISA;
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);