tree 07199519e7a2231fecef511d71aa72a1cd07b112
parent 1343bc394bb265157b2ea2d02c69cf136139a4b5
author Jonathan Zhang <jonzhang@fb.com> 1595888790 -0700
committer Angel Pons <th3fanbus@gmail.com> 1596187983 +0000

soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE

CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.

It supports DDR4.

Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.

Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>