soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 9c6450e..bd1fa97 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -68,4 +68,15 @@
select CACHE_MRC_SETTINGS
+# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
+# Default value is set to one socket, full config.
+config DIMM_MAX
+ int
+ default 12
+
+# DDR4
+config DIMM_SPD_SIZE
+ int
+ default 512
+
endif