nb/intel/pineview: Use common code for SMM in TSEG
This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.
Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25598
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 9b72ebf..6168305 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -30,6 +30,7 @@
select INTEL_GMA_ACPI
select POSTCAR_STAGE
select POSTCAR_CONSOLE
+ select SMM_TSEG
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 2647bcc..192c24e 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -27,6 +27,7 @@
#include <boot/tables.h>
#include <arch/acpi.h>
#include <northbridge/intel/pineview/pineview.h>
+#include <cpu/intel/smm/gen1/smi.h>
/* Reserve everything between A segment and 1MB:
*
@@ -141,6 +142,36 @@
add_fixed_resources(dev, index);
}
+void northbridge_write_smram(u8 smram)
+{
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ if (dev == NULL)
+ die("could not find pci 00:00.0!\n");
+
+ pci_write_config8(dev, SMRAM, smram);
+}
+
+/*
+ * Really doesn't belong here but will go away with parallel mp init,
+ * so let it be here for a while...
+ */
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+ unsigned int i;
+
+ /* Logical processors (threads) per core */
+ const struct cpuid_result cpuid1 = cpuid(1);
+ /* Read number of cores. */
+ const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+ /* TODO in parallel MP cpuid(1).ebx */
+ for (i = 0; i < cores; i++)
+ apic_id_map[i] = i;
+
+ return cores;
+}
+
static void mch_domain_set_resources(struct device *dev)
{
struct resource *res;
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index 62855c2..21b926b 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -24,6 +24,7 @@
#include <northbridge/intel/pineview/pineview.h>
#include <cpu/x86/mtrr.h>
#include <cpu/intel/romstage.h>
+#include <cpu/intel/smm/gen1/smi.h>
u8 decode_pciebar(u32 *const base, u32 *const len)
{
@@ -94,15 +95,46 @@
return (u32)(gsmsize[gsm] << 10);
}
+/** Decodes used TSEG size to bytes. */
+static u32 decode_tseg_size(const u32 esmramc)
+{
+ if (!(esmramc & 1))
+ return 0;
+
+ switch ((esmramc >> 1) & 3) {
+ case 0:
+ return 1 << 20;
+ case 1:
+ return 2 << 20;
+ case 2:
+ return 8 << 20;
+ case 3:
+ default:
+ die("Bad TSEG setting.\n");
+ }
+}
+
+u32 northbridge_get_tseg_size(void)
+{
+ const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
+ return decode_tseg_size(esmramc);
+}
+
+u32 northbridge_get_tseg_base(void)
+{
+ return pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
+}
+
+
/* Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)
{
- uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), TSEG);
- top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB);
+ uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
+
}
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
@@ -124,14 +156,14 @@
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
- /* Cache two separate 4 MiB regions below the top of ram, this
- * satisfies MTRR alignment requirements. If you modify this to
- * cover TSEG, make sure UMA region is not set with WRBACK as it
- * causes hard-to-recover boot failures.
+ /* Cache 8 MiB region below the top of ram and 2 MiB above top of
+ * ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
run_postcar_phase(&pcf);