commit de640781020b10e72dd6a5cda26cab10932e94fe
author Kyösti Mälkki <kyosti.malkki@gmail.com> Tue Dec 03 07:30:26 2019 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Sat Dec 14 14:08:57 2019 +0000
tree f3e43318b33a10918c906458e6b03b2a2194d7ee
parent 91c47c0deac054d5b949d1bf1be7c0e7cbf7d545

bootblock: Provide some common prototypes

The split of bootblock initialisation to cpu, northbridge and
southbridge is not specific to intel at all, create new header
<arch/bootblock.h> as AMD will want some of these too.

Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/southbridge/intel/i82371eb/bootblock.c

diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index a6d62e0..711b317 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -15,10 +15,10 @@
  */
 
 #include <stdint.h>
+#include <arch/bootblock.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>
-#include <cpu/intel/car/bootblock.h>
 #include "i82371eb.h"
 
 #define PCI_ID(VENDOR_ID, DEVICE_ID) \