cpu/amd/fam10: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index d74d6de..e0e3ca1 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -210,8 +210,7 @@
static inline bool cpu_is_amd(void)
{
- return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)
- || CONFIG(SOC_AMD_COMMON) || CONFIG(CPU_AMD_MODEL_10XXX);
+ return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI) || CONFIG(SOC_AMD_COMMON);
}
static inline bool cpu_is_intel(void)
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index 725d808..7e05408 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -545,16 +545,6 @@
return 0x13;
if (CONFIG(CPU_INTEL_SOCKET_LGA775))
return 0x15;
- if (CONFIG(CPU_AMD_SOCKET_AM2R2))
- return 0x17;
- if (CONFIG(CPU_AMD_SOCKET_F_1207))
- return 0x18;
- if (CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA))
- return 0x1a;
- if (CONFIG(CPU_AMD_SOCKET_AM3))
- return 0x1b;
- if (CONFIG(CPU_AMD_SOCKET_C32_NON_AGESA))
- return 0x1c;
return 0x02; /* Unknown */
}
diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig
index 7a6d956..4ade0f6 100644
--- a/src/cpu/amd/Kconfig
+++ b/src/cpu/amd/Kconfig
@@ -1,12 +1,2 @@
-source src/cpu/amd/socket_AM2r2/Kconfig
-source src/cpu/amd/socket_AM3/Kconfig
-source src/cpu/amd/socket_C32/Kconfig
-source src/cpu/amd/socket_FM2/Kconfig
-source src/cpu/amd/socket_G34/Kconfig
-source src/cpu/amd/socket_ASB2/Kconfig
-source src/cpu/amd/socket_F_1207/Kconfig
-
-source src/cpu/amd/family_10h-family_15h/Kconfig
-
source src/cpu/amd/agesa/Kconfig
source src/cpu/amd/pi/Kconfig
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 72c6aa2..5c07a66 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -1,10 +1,2 @@
-subdirs-$(CONFIG_CPU_AMD_SOCKET_F_1207) += socket_F_1207
-subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
-subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
-subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
-subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
-subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2
-subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34
-
subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
subdirs-$(CONFIG_CPU_AMD_PI) += pi
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
deleted file mode 100644
index 2054ea3..0000000
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ /dev/null
@@ -1,648 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase CONFIG_DCACHE_RAM_BASE
-#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE
-#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH
-
-/* For CAR with Fam10h. */
-#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE
-
-#define jmp_if_not_k8(x) comisd %xmm2, %xmm1; jae x
-#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
-#define jmp_if_not_fam15h(x) comisd %xmm3, %xmm1; jb x
-#define jmp_if_fam15h(x) comisd %xmm3, %xmm1; jae x
-
-#define CPUID_MASK 0x0ff00f00
-#define CPUID_VAL_FAM10_ROTATED 0x0f000010
-#define CPUID_VAL_FAM15_ROTATED 0x0f000060
-
-/*
- * XMM map:
- * xmm1: CPU family
- * xmm2: Fam10h comparison value
- * xmm3: Fam15h comparison value
- * xmm4: Backup EBX
- * xmm5: coreboot init detect
- */
-
- /* Save the BIST result. */
- movl %eax, %ebp
-
- /*
- * For normal part %ebx already contain cpu_init_detected
- * from fallback call.
- */
-
-cache_as_ram_setup:
- post_code(0xa0)
-
- /* Enable SSE. */
- movl %cr4, %eax
- orl $(3 << 9), %eax
- movl %eax, %cr4
-
- /* Figure out the CPU family. */
- cvtsi2sd %ebx, %xmm4
- movl $0x01, %eax
- cpuid
- /* Base family is bits 8..11, extended family is bits 20..27. */
- andl $CPUID_MASK, %eax
- /* Reorder bits for easier comparison by value. */
- roll $0x10, %eax
- cvtsi2sd %eax, %xmm1
- movl $CPUID_VAL_FAM10_ROTATED, %eax
- cvtsi2sd %eax, %xmm2
- movl $CPUID_VAL_FAM15_ROTATED, %eax
- cvtsi2sd %eax, %xmm3
- cvtsd2si %xmm4, %ebx
-
- /* Check if cpu_init_detected. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- andl $MTRR_DEF_TYPE_EN, %eax
- movl %eax, %ebx /* We store the status. */
- cvtsi2sd %ebx, %xmm5
-
- jmp_if_k8(CAR_FAM10_out_post_errata)
-
- /*
- * For GH, CAR need to set DRAM Base/Limit registers to direct that
- * to node0.
- * Only BSP needed, for other nodes set during HT/memory init.
- * So we need to check if it is BSP.
- */
- movl $0x1b, %ecx
- rdmsr
- bt $8, %eax /* BSP */
- jnc CAR_FAM10_out
-
- /* Enable RT tables on BSP. */
- movl $0x8000c06c, %eax
- movw $0xcf8, %dx
- outl %eax, %dx
- addw $4, %dx
- inl %dx, %eax
- btr $0, %eax
- outl %eax, %dx
-
- /* Setup temporary DRAM map: [0,16M) bit 0-23. */
- movl $0x8000c144, %eax
- movw $0xcf8, %dx
- outl %eax, %dx
- addw $4, %dx
- movl $0, %eax
- outl %eax, %dx
-
- movl $0x8000c140, %eax
- movw $0xcf8, %dx
- outl %eax, %dx
- addw $4, %dx
- movl $3, %eax
- outl %eax, %dx
-
-CAR_FAM10_out:
-
- jmp_if_fam15h(CAR_FAM10_errata_applied)
- /*
- * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
- * Re-enable it in after RAM is initialized and before CAR is disabled.
- */
- movl $BU_CFG2_MSR, %ecx
- rdmsr
- bts $15, %eax /* Set bit 15 in EDX:EAX (bit 15 in EAX). */
- wrmsr
-
- /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
- movl $BU_CFG2_MSR, %ecx
- rdmsr
- bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
- wrmsr
-
-CAR_FAM10_errata_applied:
-
-#if CONFIG(MMCONF_SUPPORT)
- #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
- #error "MMCONF_BASE_ADDRESS too big"
- #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
- #error "MMCONF_BASE_ADDRESS not 1MB aligned"
- #endif
- movl $0, %edx
- movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
- #if (CONFIG_MMCONF_BUS_NUMBER == 1)
- #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
- orl $(1 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
- orl $(2 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
- orl $(3 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
- orl $(4 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 32)
- orl $(5 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 64)
- orl $(6 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 128)
- orl $(7 << 2), %eax
- #elif (CONFIG_MMCONF_BUS_NUMBER == 256)
- orl $(8 << 2), %eax
- #else
- #error "bad MMCONF_BUS_NUMBER value"
- #endif
- movl $MMIO_CONF_BASE, %ecx
- wrmsr
-#endif
-
-CAR_FAM10_out_post_errata:
-
- /* Fam15h APIC IDs do not depend on NB config bit 54 */
- jmp_if_not_fam15h(skip_nb54_set)
- movl $NB_CFG_MSR, %ecx
- rdmsr
- bts $(54 - 32), %edx /* Set NB config bit 54 */
- wrmsr
-
-skip_nb54_set:
- /* On Fam15h CPUs each compute unit's MTRRs are shared between two cores */
- jmp_if_not_fam15h(skip_cu_check)
-
- /* Get the initial APIC ID. */
- movl $1, %eax
- cpuid
- movl %ebx, %eax
-
- /* Restore init detect */
- cvtsd2si %xmm5, %ebx
-
- /* Determine if this is the second core to start in a compute unit; if so, wait for first core start, clear init detect and skip MTRR init */
- bt $24, %eax
- jnc skip_cu_check /* First core in the compute unit jumps to skip_cu_check */
-
- /* Determine if this is the second core to start in a compute unit; if so, clear init detect and skip MTRR init */
- /* Busywait until the first core sets up the MTRRs */
-check_init_detect_1:
- /* Check if cpu_init_detected. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- rdmsr
- andl $MTRR_DEF_TYPE_EN, %eax
- cmp $0x00000000, %eax
- je check_init_detect_1 /* First core has not yet started */
-
-check_init_detect_2:
- movl $SYSCFG_MSR, %ecx
- rdmsr
- andl $(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn), %eax
- cmp $0x00000000, %eax
- je check_init_detect_2 /* First core has not yet started */
-
- /* First core has now started */
- movl $0x00000000, %ebx /* Clear init detect flag */
- cvtsi2sd %ebx, %xmm5
- jmp fam10_mtrr_setup_complete
-
-skip_cu_check:
-
- jmp_if_not_fam15h(CAR_FAM15_errata_applied)
-
- /* Erratum 714, RevGuide for Fam15h, Pub#48063 Rev. 3.24 */
- movl $BU_CFG2_MSR, %ecx
- rdmsr
- bts $8, %eax /* Set bit 8 in EDX:EAX (bit 8 in EAX). */
- wrmsr
-
-CAR_FAM15_errata_applied:
-
- /* Set MtrrFixDramModEn for clear fixed MTRR. */
-enable_fixed_mtrr_dram_modify:
- movl $SYSCFG_MSR, %ecx
- rdmsr
- andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
- orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
- wrmsr
-
- /* Clear all MTRRs. */
- xorl %edx, %edx
- movl $all_mtrr_msrs, %esi
-
-clear_fixed_var_mtrr:
- lodsl (%esi), %eax
- testl %eax, %eax
- jz clear_fixed_var_mtrr_out
-
- movl %eax, %ecx
- xorl %eax, %eax
- wrmsr
-
- jmp clear_fixed_var_mtrr
-clear_fixed_var_mtrr_out:
-
-/*
- * 0x06 is the WB IO type for a given 4k segment.
- * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
- * segs is the number of 4k segments in the area of the particular
- * register we want to use for CAR.
- * reg is the register where the IO type should be stored.
- */
-.macro extractmask segs, reg
-.if \segs <= 0
- /*
- * The xorl here is superfluous because at the point of first execution
- * of this macro, %eax and %edx are cleared. Later invocations of this
- * macro will have a monotonically increasing segs parameter.
- */
- xorl \reg, \reg
-.else
- jmp_if_k8(1f)
-
-.if \segs == 1
- movl $0x1e000000, \reg /* WB MEM type */
-.elseif \segs == 2
- movl $0x1e1e0000, \reg /* WB MEM type */
-.elseif \segs == 3
- movl $0x1e1e1e00, \reg /* WB MEM type */
-.elseif \segs >= 4
- movl $0x1e1e1e1e, \reg /* WB MEM type */
-.endif
- jmp 2f
-1:
-.if \segs == 1
- movl $0x06000000, \reg /* WB IO type */
-.elseif \segs == 2
- movl $0x06060000, \reg /* WB IO type */
-.elseif \segs == 3
- movl $0x06060600, \reg /* WB IO type */
-.elseif \segs >= 4
- movl $0x06060606, \reg /* WB IO type */
-.endif
-2:
-.endif /* if \segs <= 0 */
-.endm
-
-/*
- * carsize is the cache size in bytes we want to use for CAR.
- * windowoffset is the 32k-aligned window into CAR size.
- */
-.macro simplemask carsize, windowoffset
- .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12) - 4)
- extractmask gas_bug_workaround, %eax
- .set gas_bug_workaround,(((\carsize - \windowoffset) >> 12))
- extractmask gas_bug_workaround, %edx
- /*
- * Without the gas bug workaround, the entire macro would consist
- * only of the two lines below:
- * extractmask (((\carsize - \windowoffset) >> 12) - 4), %eax
- * extractmask (((\carsize - \windowoffset) >> 12)), %edx
- */
-.endm
-
-#if CONFIG(CPU_AMD_MODEL_10XXX)
- #if CacheSize > 0x80000
- #error Invalid CAR size, must be at most 128k (processor limit is 512k).
- #endif
-#else
- #if CacheSize > 0x10000
- #error Invalid CAR size, must be at most 64k.
- #endif
-#endif
-#if CacheSize < 0x1000
-#error Invalid CAR size, must be at least 4k. This is a processor limitation.
-#endif
-#if (CacheSize & (0x1000 - 1))
-#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
-#endif
-
-#if CacheSize > 0x8000
- /* Enable caching for 32K-64K using fixed MTRR. */
- movl $MTRR_FIX_4K_C0000, %ecx
- simplemask CacheSize, 0x8000
- wrmsr
-#endif
-
-#if CacheSize > 0x10000
- /* Enable caching for 64K-96K using fixed MTRR. */
- movl $MTRR_FIX_4K_D0000, %ecx
- simplemask CacheSize, 0x10000
- wrmsr
-#endif
-
-#if CacheSize > 0x18000
- /* Enable caching for 96K-128K using fixed MTRR. */
- movl $MTRR_FIX_4K_D8000, %ecx
- simplemask CacheSize, 0x18000
- wrmsr
-#endif
-
- /* Enable caching for 0-32K using fixed MTRR. */
- movl $MTRR_FIX_4K_C8000, %ecx
- simplemask CacheSize, 0
- wrmsr
-
- jmp_if_fam15h(fam15_skip_dram_mtrr_setup)
-
- /* Enable memory access for first MBs using top_mem. */
- movl $TOP_MEM, %ecx
- xorl %edx, %edx
- movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
- wrmsr
-
-fam15_skip_dram_mtrr_setup:
-
-#if CONFIG_XIP_ROM_SIZE
-
- /* Enable write base caching so we can do execute in place (XIP)
- * on the flash ROM.
- */
- movl $MTRR_PHYS_BASE(1), %ecx
- xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
- */
- movl $_program, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
- orl $MTRR_TYPE_WRBACK, %eax
- wrmsr
-
- movl $MTRR_PHYS_MASK(1), %ecx
- movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
- jmp_if_k8(wbcache_post_fam10_setup)
- movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
-wbcache_post_fam10_setup:
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
- wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE */
-
- /* Set the default memory type and enable fixed and variable MTRRs. */
- movl $MTRR_DEF_TYPE_MSR, %ecx
- xorl %edx, %edx
- movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
- wrmsr
-
- /* Enable the MTRRs and IORRs in SYSCFG. */
- movl $SYSCFG_MSR, %ecx
- rdmsr
- orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
- wrmsr
-
-fam10_mtrr_setup_complete:
- post_code(0xa1)
-
- /* Disable conversion of INVD to WBINVD (INVDWBINVD = 0) */
- mov $HWCR_MSR, %ecx
- rdmsr
- btr $4, %eax
- wrmsr
-
-jmp_if_not_fam15h(fam15_car_msr_setup_complete)
- /* Disable streaming store (DisSS = 1) */
- mov $LS_CFG_MSR, %ecx
- rdmsr
- bts $28, %eax
- wrmsr
-
- /* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
- mov $IC_CFG_MSR, %ecx
- rdmsr
- bts $9, %eax
- wrmsr
-
- /* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
- mov $DC_CFG_MSR, %ecx
- rdmsr
- bts $4, %eax
- bts $13, %eax
- wrmsr
-
- /* Disable CR0 combining (CombineCr0Cd = 0) */
- mov $BU_CFG3_MSR, %ecx
- rdmsr
- btr $49-32, %edx
- wrmsr
-fam15_car_msr_setup_complete:
-
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- movl %eax, %cr0
-
- jmp_if_not_k8(CAR_skip_k8_errata_part1)
-
- /* Set DisFillP on BSP. */
- movl $0x8000c068, %eax
- movw $0xcf8, %dx
- outl %eax, %dx
- addw $4, %dx
- inl %dx, %eax
- bts $10, %eax
- outl %eax, %dx
-
-CAR_skip_k8_errata_part1:
-
- jmp_if_k8(fam10_end_part1)
-
- /* So we need to check if it is BSP. */
- movl $0x1b, %ecx
- rdmsr
- bt $8, %eax /* BSP */
- jnc CAR_FAM10_ap
-fam10_end_part1:
-
- post_code(0xa2)
-
- /* Read the range with lodsl. */
- cld
- movl $CacheBase, %esi
- movl $(CacheSize >> 2), %ecx
- rep lodsl
-
- /* Clear the range. */
- movl $CacheBase, %edi
- movl $(CacheSize >> 2), %ecx
- xorl %eax, %eax
- rep stosl
-
- jmp_if_not_k8(CAR_skip_k8_errata_part2)
-
- /* Clear DisFillP on BSP. */
- movl $0x8000c068, %eax
- movw $0xcf8, %dx
- outl %eax, %dx
- addw $4, %dx
- inl %dx, %eax
- btr $10, %eax
- outl %eax, %dx
-
-CAR_skip_k8_errata_part2:
-
- /* Set up the stack pointer. */
- movl $(CacheBase + CacheSize), %eax
- movl %eax, %esp
-
- /* Poison the lower stack boundary */
- movl $((CacheBase + CacheSize) - CacheSizeBSPStack), %eax
- movl $0xdeadbeef, (%eax)
-
- post_code(0xa3)
-
- jmp CAR_FAM10_ap_out
-CAR_FAM10_ap:
- /*
- * Need to set stack pointer for AP.
- * It will be from:
- * CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))
- * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
- * The spacing between the BSP stack and the top of the AP
- * stacks is purposefully set larger (an extra CacheSizeBSPSlush
- * worth of unused space) than necessary to aid debugging when
- * additional stack variables are added by future developers.
- * The extra space will allow BSP overruns to be caught by
- * the warning logic and easily fixed instead of crashing the
- * system with no obvious clues of what went wrong.
- *
- * So, need to get the NodeID and CoreID at first.
- * If NB_CFG_MSR bit 54 is set just use initial APIC ID, otherwise need
- * to reverse it.
- */
-
- /* Get the coreid bits at first. */
- movl $0x80000008, %eax
- cpuid
- shrl $12, %ecx
- andl $0x0f, %ecx
- movl %ecx, %edi
-
- /* Get the initial APIC ID. */
- movl $1, %eax
- cpuid
- shrl $24, %ebx
-
- /* Get the nb cfg bit 54. */
- movl $NB_CFG_MSR, %ecx
- rdmsr
- movl %edi, %ecx /* CoreID bits */
- bt $(54 - 32), %edx
- jc roll_cfg
-
- /* Fam10h NB config bit 54 was not set */
- rolb %cl, %bl
-roll_cfg:
- jmp_if_not_fam15h(ap_apicid_ready)
- cmp $0x5, %ecx
- jne ap_apicid_ready
-
- /* This is a multi-node CPU
- * Adjust the maximum APIC ID to a more reasonable value
- * given that no 32-core Family 15h processors exist
- */
- movl %ebx, %ecx
- and $0x0f, %ecx /* Get lower 4 bits of CPU number */
- and $0x60, %ebx /* Get node ID */
- shrl $0x1, %ebx /* Shift node ID part of APIC ID down by 1 */
- or %ecx, %ebx /* Recombine node ID and CPU number */
-
-ap_apicid_ready:
-
- /* Calculate stack pointer using adjusted APIC ID stored in ebx */
- movl $CacheSizeAPStack, %eax
- mull %ebx
- movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp
- subl %eax, %esp
-
- /* Restore init detect */
- cvtsd2si %xmm5, %ebx
-
- post_code(0xa4)
-
-CAR_FAM10_ap_out:
-
- post_code(0xa5)
-
- /* Disable SSE. */
- movl %cr4, %eax
- andl $~(3 << 9), %eax
- movl %eax, %cr4
-
- post_code(0xa6)
-
- /* Restore the BIST result. */
- movl %ebp, %eax
-
- /* We need to set EBP? No need. */
- movl %esp, %ebp
- pushl %ebx /* Init detected. */
- pushl %eax /* BIST */
-
- post_code(0xa7)
-
- call cache_as_ram_main
-
- call post_cache_as_ram
- movl %eax, %esp
-
- call cache_as_ram_new_stack
-
- /* We will not go back. */
-
- post_code(0xaf) /* Should never see this POST code. */
-
-all_mtrr_msrs:
- /* fixed MTRR MSRs */
- .long MTRR_FIX_64K_00000
- .long MTRR_FIX_16K_80000
- .long MTRR_FIX_16K_A0000
- .long MTRR_FIX_4K_C0000
- .long MTRR_FIX_4K_C8000
- .long MTRR_FIX_4K_D0000
- .long MTRR_FIX_4K_D8000
- .long MTRR_FIX_4K_E0000
- .long MTRR_FIX_4K_E8000
- .long MTRR_FIX_4K_F0000
- .long MTRR_FIX_4K_F8000
-
- /* var MTRR MSRs */
- .long MTRR_PHYS_BASE(0)
- .long MTRR_PHYS_MASK(0)
- .long MTRR_PHYS_BASE(1)
- .long MTRR_PHYS_MASK(1)
- .long MTRR_PHYS_BASE(2)
- .long MTRR_PHYS_MASK(2)
- .long MTRR_PHYS_BASE(3)
- .long MTRR_PHYS_MASK(3)
- .long MTRR_PHYS_BASE(4)
- .long MTRR_PHYS_MASK(4)
- .long MTRR_PHYS_BASE(5)
- .long MTRR_PHYS_MASK(5)
- .long MTRR_PHYS_BASE(6)
- .long MTRR_PHYS_MASK(6)
- .long MTRR_PHYS_BASE(7)
- .long MTRR_PHYS_MASK(7)
-
- /* Variable IORR MTRR MSRs */
- .long IORRBase_MSR(0)
- .long IORRMask_MSR(0)
- .long IORRBase_MSR(1)
- .long IORRMask_MSR(1)
-
- /* Top of memory MTRR MSRs */
- .long TOP_MEM
- .long TOP_MEM2
-
- .long 0x000 /* NULL, end of table */
-
-cache_as_ram_setup_out:
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
deleted file mode 100644
index fb632bb..0000000
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * WARNING: this file will be used by both any AP cores and core 0 / node 0
- */
-
-#include <arch/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-
-static __always_inline uint32_t amd_fam1x_cpu_family(void)
-{
- uint32_t family;
-
- family = cpuid_eax(0x80000001);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- return family;
-}
-
-static __always_inline
-void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
-{
- msr_t msr;
- uint32_t family;
-
- if (!skip_sharedc_config) {
- /* disable cache */
- write_cr0(read_cr0() | CR0_CacheDisable);
-
- msr.lo = 0;
- msr.hi = 0;
- wrmsr(MTRR_FIX_4K_C8000, msr);
- if (CONFIG_DCACHE_RAM_SIZE > 0x8000)
- wrmsr(MTRR_FIX_4K_C0000, msr);
- if (CONFIG_DCACHE_RAM_SIZE > 0x10000)
- wrmsr(MTRR_FIX_4K_D0000, msr);
- if (CONFIG_DCACHE_RAM_SIZE > 0x18000)
- wrmsr(MTRR_FIX_4K_D8000, msr);
-
- /* disable fixed mtrr from now on,
- * it will be enabled by ramstage again
- */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn
- | SYSCFG_MSR_MtrrFixDramModEn);
- wrmsr(SYSCFG_MSR, msr);
-
- /* Set the default memory type and
- * disable fixed and enable variable MTRRs
- */
- msr.hi = 0;
- msr.lo = (1 << 11);
-
- wrmsr(MTRR_DEF_TYPE_MSR, msr);
-
- enable_cache();
- }
-
- /* INVDWBINVD = 1 */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (0x1 << 4);
- wrmsr(HWCR_MSR, msr);
-
- family = amd_fam1x_cpu_family();
-
-#if CONFIG(CPU_AMD_MODEL_10XXX)
- if (family >= 0x6f) {
- /* Family 15h or later */
-
- /* DisSS = 0 */
- msr = rdmsr(LS_CFG_MSR);
- msr.lo &= ~(0x1 << 28);
- wrmsr(LS_CFG_MSR, msr);
-
- if (!skip_sharedc_config) {
- /* DisSpecTlbRld = 0 */
- msr = rdmsr(IC_CFG_MSR);
- msr.lo &= ~(0x1 << 9);
- wrmsr(IC_CFG_MSR, msr);
-
- /* Erratum 714: SpecNbReqDis = 0 */
- msr = rdmsr(BU_CFG2_MSR);
- msr.lo &= ~(0x1 << 8);
- wrmsr(BU_CFG2_MSR, msr);
- }
-
- /* DisSpecTlbRld = 0 */
- /* DisHwPf = 0 */
- msr = rdmsr(DC_CFG_MSR);
- msr.lo &= ~(0x1 << 4);
- msr.lo &= ~(0x1 << 13);
- wrmsr(DC_CFG_MSR, msr);
- }
-#endif
-}
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
deleted file mode 100644
index 78e417f..0000000
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/stages.h>
-#include <arch/early_variables.h>
-#include <commonlib/helpers.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/msr.h>
-#include <arch/acpi.h>
-#include <program_loading.h>
-#include <romstage_handoff.h>
-
-#include "cpu/amd/car/disable_cache_as_ram.c"
-
-// For set_sysinfo_in_ram()
-#include <northbridge/amd/amdfam10/raminit.h>
-
-#if CONFIG_RAMTOP <= 0x100000
- #error "You need to set CONFIG_RAMTOP greater than 1M"
-#endif
-
-#if CONFIG(DEBUG_CAR)
-#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)
-#else
-#define print_car_debug(format, arg...)
-#endif
-
-static void memcpy_(void *d, const void *s, size_t len)
-{
- print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...",
- (uint32_t) s, (uint32_t) (s + len - 1),
- (uint32_t) d, (uint32_t) (d + len - 1));
- memcpy(d, s, len);
-}
-
-static int memcmp_(void *d, const void *s, size_t len)
-{
- print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...",
- (uint32_t) s, (uint32_t) (s + len - 1),
- (uint32_t) d, (uint32_t) (d + len - 1));
- return memcmp(d, s, len);
-}
-
-/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33
- * and RevGuide for Fam12h, Pub#44739 Rev 3.10
- */
-
-static void vErrata343(void)
-{
- msr_t msr;
- unsigned int uiMask = 0xFFFFFFF7;
-
- msr = rdmsr(BU_CFG2_MSR);
- msr.hi &= uiMask; // IcDisSpecTlbWr (bit 35) = 0
- wrmsr(BU_CFG2_MSR, msr);
-}
-
-asmlinkage void *post_cache_as_ram(void)
-{
- uint32_t family = amd_fam1x_cpu_family();
- int s3resume = 0;
-
- /* Verify that the BSP didn't overrun the lower stack
- * boundary during romstage execution
- */
- volatile uint32_t *lower_stack_boundary;
- lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) -
- CONFIG_DCACHE_BSP_TOP_STACK_SIZE);
-
- if ((*lower_stack_boundary) != 0xdeadbeef)
- printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
-
-
- /* ACPI S3 is not supported without RELOCATABLE_RAMSTAGE and
- * this will always return 0. */
- s3resume = acpi_is_wakeup_s3();
-
- romstage_handoff_init(s3resume);
-
- /* from here don't store more data in CAR */
- if (family >= 0x1f && family <= 0x3f) {
- /* Family 10h and 12h, 11h until shown otherwise */
- vErrata343();
- }
-
- size_t car_size = car_data_size();
- void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
-
- print_car_debug("Copying data from cache to RAM...");
- memcpy_(migrated_car, _car_global_start, car_size);
- print_car_debug(" Done\n");
-
- print_car_debug("Verifying data integrity in RAM...");
- if (memcmp_(migrated_car, _car_global_start, car_size) == 0)
- print_car_debug(" Done\n");
- else
- print_car_debug(" FAILED\n");
-
- /* New stack grows right below migrated_car. */
- print_car_debug("Switching to use RAM as stack...");
- return migrated_car;
-}
-
-asmlinkage void cache_as_ram_new_stack(void)
-{
- print_car_debug("Disabling cache as RAM now\n");
- disable_cache_as_ram_real(0); // inline
-
- disable_cache();
- /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
- set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
- enable_cache();
-
- set_sysinfo_in_ram(1); // So other core0 could start to train mem
-
- /*copy and execute ramstage */
- copy_and_run();
- /* We will not return */
-
- print_car_debug("should not be here -\n");
-}
diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
deleted file mode 100644
index ad4f5f4..0000000
--- a/src/cpu/amd/family_10h-family_15h/Kconfig
+++ /dev/null
@@ -1,90 +0,0 @@
-config CPU_AMD_MODEL_10XXX
- bool
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
- select SSE2
- select TSC_SYNC_LFENCE
- select UDELAY_LAPIC
- select SUPPORT_CPU_UCODE_IN_CBFS
- select CPU_MICROCODE_MULTIPLE_FILES
- select CAR_GLOBAL_MIGRATION
-
-if CPU_AMD_MODEL_10XXX
-
-config USE_LARGE_DCACHE
- bool
- default y if CPU_AMD_SOCKET_G34_NON_AGESA
- default y if CPU_AMD_SOCKET_FM2_NON_AGESA
- default y if CPU_AMD_SOCKET_C32_NON_AGESA
- default n
-
-config NUM_IPI_STARTS
- int
- default 1
-
-config CPU_ADDR_BITS
- int
- default 48
-
-config DCACHE_RAM_BASE
- hex
- default 0xc4000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x0c000
-
-config DCACHE_BSP_TOP_STACK_SIZE
- hex
- default 0x4000
-
-config DCACHE_BSP_TOP_STACK_SLUSH
- hex
- default 0x4000 if USE_LARGE_DCACHE
- default 0x1000
-
-config DCACHE_AP_STACK_SIZE
- hex
- default 0x500
-
-config SET_FIDVID
- bool
- default y
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config LIFT_BSP_APIC_ID
- bool
- default n
-
-if SET_FIDVID
-config SET_FIDVID_DEBUG
- bool
- default y
-
-config SET_FIDVID_STORE_AP_APICID_AT_FIRST
- bool
- default y
-
-config SET_FIDVID_CORE0_ONLY
- bool
- default n
-
-# 0: all cores
-# 1: core 0 only
-# 2: all but core 0
-config SET_FIDVID_CORE_RANGE
- int
- default 0
-
-endif # SET_FIDVID
-
-config UDELAY_LAPIC_FIXED_FSB
- int
- default 200
-
-endif # CPU_AMD_MODEL_10XXX
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
deleted file mode 100644
index 7035323..0000000
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ /dev/null
@@ -1,25 +0,0 @@
-romstage-y += ../../x86/mtrr/earlymtrr.c
-romstage-y += ../car/post_cache_as_ram.c
-
-romstage-y += init_cpus.c
-
-ramstage-y += model_10xxx_init.c
-ramstage-y += processor_name.c
-
-romstage-y += update_microcode.c
-romstage-y += tsc_freq.c
-ramstage-y += tsc_freq.c
-romstage-y += ram_calc.c
-ramstage-y += ram_calc.c
-ramstage-y += monotonic_timer.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
-
-# Microcode for Family 10h, 11h, 12h, and 14h
-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
-microcode_amd.bin-type := microcode
-
-# Microcode for Family 15h
-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
-microcode_amd_fam15h.bin-type := microcode
diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h
deleted file mode 100644
index 6b9cd19..0000000
--- a/src/cpu/amd/family_10h-family_15h/defaults.h
+++ /dev/null
@@ -1,834 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/amdmct/amddefs.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/msr.h>
-
-/*
- * Default MSR and errata settings.
- */
-static const struct {
- u32 msr;
- uint64_t revision;
- u32 platform;
- u32 data_lo;
- u32 data_hi;
- u32 mask_lo;
- u32 mask_hi;
-} fam10_msr_default[] = {
- { TOP_MEM2, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00000000, 0x00000000,
- 0xFFFFFFFF, 0xFFFFFFFF },
-
- { SYSCFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 3 << 21, 0x00000000,
- 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
-
- { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL,
- 1 << 18, 0x00000000,
- 1 << 18, 0x00000000 }, /* Erratum 586: [DEIBP]=1 */
-
- { MC1_CTL_MASK, AMD_OR_B2, AMD_PTYPE_ALL,
- 1 << 15, 0x00000000,
- 1 << 15, 0x00000000 }, /* Erratum 593: [BSRP]=1 */
-
- { MC1_CTL_MASK, AMD_OR_C0, AMD_PTYPE_ALL,
- 1 << 15, 0x00000000,
- 1 << 15, 0x00000000 }, /* Erratum 739: [BSRP]=1 */
-
- { 0xc0011000, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 1 << 16, 0x00000000,
- 1 << 16, 0x00000000 }, /* Erratum 608: [bit 16]=1 */
-
- { 0xc0011000, AMD_OR_C0, AMD_PTYPE_ALL,
- 1 << 15, 0x00000000,
- 1 << 15, 0x00000000 }, /* Erratum 727: [bit 15]=1 */
-
- { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0xF << 19, 0x00000000,
- 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */
-
- { MC4_CTL_MASK, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 1 << 10, 0x00000000,
- 1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */
-
- { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_SVR,
- 0x00000000, 0x00000004,
- 0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */
-
- { DC_CFG_MSR, AMD_DR_Bx, AMD_PTYPE_SVR,
- 0x00000000, 0x00000000,
- 0x00000000, 0x00000C00 }, /* Erratum 326 */
-
- { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
- 0x00000000, 1 << 22,
- 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
-
- { NB_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
- 1 << 23, 0x00000000,
- 1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */
-
- { BU_CFG2_MSR, AMD_DR_Bx, AMD_PTYPE_ALL,
- 1 << 29, 0x00000000,
- 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
-
- { DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 1 << 24, 0x00000000,
- 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
-
- { LS_CFG_MSR, AMD_DR_GT_B0, AMD_PTYPE_ALL,
- 0 << 1, 0x00000000,
- 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
-
- { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 0x00000000, 1 << (39-32),
- 0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */
-
- { IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 0xf << 1, 0x00000000,
- 0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */
-
- { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
- 1 << 21, 0x00000000,
- 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */
-
- { BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
- 1 << 23, 0x00000000,
- 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG_MSR[23]=1 */
-
- { BU_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0 << 10, 0x00000000,
- 1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */
-
- /* CPUID_EXT_FEATURES */
- { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
- 1 << 28, 0x00000000,
- 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
-
- { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC,
- 0x00000000, 1 << (33-32),
- 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
-
- { DE_CFG_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
- 1 << 10, 0x00000000,
- 1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */
-
- { BU_CFG2_MSR, AMD_DRBH_Cx, AMD_PTYPE_ALL,
- 0x00000000, 1 << (35-32),
- 0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
-
- { BU_CFG3_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
- 0x00000000, 1 << (42-32),
- 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */
-
- { BU_CFG3_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 1 << 22, 0x00000000,
- 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */
-
- { EX_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 0x00000000, 1 << (54-32),
- 0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */
-
- { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 1 << 23, 0x00000000,
- 1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */
-
- { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 1 << 14, 0x00000000,
- 1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */
-
- { LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
- 1 << 12, 0x00000000,
- 1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */
-
- { OSVW_ID_Length, AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL,
- 0x00000004, 0x00000000,
- 0x00000004, 0x00000000}, /* B0 or Above, OSVW_ID_Length is 0004h */
-
- { OSVW_Status, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_MC,
- 0x0000000C, 0x00000000,
- 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */
-
- { OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000005, 0x00000000,
- 0x0000ffff, 0x00000000}, /* OSVW_ID_Length = 0x5 */
-
- { OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000010, 0x00000000,
- 0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */
-
- { BU_CFG2_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
- 0x00000000, 1 << (50-32),
- 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/
-
- { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x0 << (36-32),
- 0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */
-
- { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 1 << 10, 0x00000000,
- 1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */
-
- { BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 1 << 11, 0x00000000,
- 1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */
-
- { CPU_ID_EXT_FEATURES_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
- 0x00000000, 1 << (51 - 32),
- 0x00000000, 1 << (51 - 32)}, /* G34_PKG | C32_PKG | S1G4_PKG | ASB2_PKG */
-
- { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000000, 1 << (56 - 32),
- 0x00000000, 1 << (56 - 32)}, /* [PerfCtrExtNB]=1 */
-
- { CPU_ID_EXT_FEATURES_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000000, 1 << (55 - 32),
- 0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */
-
- { IBS_OP_DATA3_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0 << 16, 0x00000000,
- 1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */
-
- { MC4_MISC0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x1 << (52-32),
- 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
-
- { MC4_MISC1, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x1 << (52-32),
- 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
-
- { MC4_MISC2, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x1 << (52-32),
- 0x00000000, 0xf << (52-32)}, /* [LvtOffset]=1 */
-};
-
-
-/*
- * Default PCI and errata settings.
- */
-static const struct {
- u8 function;
- u16 offset;
- uint64_t revision;
- u32 platform;
- u32 data;
- u32 mask;
-} fam10_pci_default[] = {
-
- /* Function 0 - HT Config */
- { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x000e0000, 0x000e0000 }, /* [19:17] for 8bit APIC config */
-
- { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00400000, 0x00600000 }, /* [22:21] DsNpReqLmt = 10b */
-
- { 0, 0x68, AMD_FAM10_LT_D, AMD_PTYPE_ALL,
- 0x00004000, 0x00006000 }, /* [14:13] BufRelPri = 2h */
-
- { 0, 0x68, (AMD_FAM10_REV_D | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00002000, 0x00006000 }, /* [14:13] BufRelPri = 1h */
-
- { 0, 0x68, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00000800, 0x00000800 }, /* [11] RspPassPW = 1 */
-
- /* Errata 281 Workaround */
- { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
- AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */
-
- { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
-
- { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
-
- { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
-
- { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
-
- /* Link Global Retry Control Register */
- { 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7,
- HtRetryCrcDatInsDynEn = 0x1,
- HtRetryCrcCmdPackDynEn = 0x1,
- HtRetryCrcDatIns = 0x4,
- HtRetryCrcCmdPack = 0x1,
- ForceErrType = 0x0,
- MultRetryErr = 0x0 */
-
- /* Errata 600 */
- { 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL,
- 0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */
-
- /* Errata 351
- * System software should program the Link Extended Control Registers[LS2En]
- * (F0x[18C:170][8]) to 0b for all links. System software should also
- * program Link Global Extended Control Register[ForceFullT0]
- * (F0x16C[15:13]) to 000b */
-
- { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
- 0x00000000, 0x00000100 },
- { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
- { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
- { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
- { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
- { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
- { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
- { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0x00000100 },
-
- /* Link Global Extended Control Register */
- { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
- * Set T0Time 14h per BKDG */
-
- { 0, 0x170, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x174, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x178, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x17C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x180, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x184, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
- { 0, 0x18C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 },
-
- /* Link Global Extended Control Register */
- { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 111b,
- * Set T0Time 26h per BKDG */
-
- { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x7 << 13, 0x7 << 13 }, /* [15:13] ForceFullT0 = 7h */
-
- { 0, 0x16C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x26, 0x3f }, /* [5:0] T0Time = 26h */
-
-
- /* Function 1 - Map Init */
-
- /* Before reading F1x114_x2 or F1x114_x3 software must
- * initialize the registers or NB Array MCA errors may
- * occur. BIOS should initialize index 0h of F1x114_x2 and
- * F1x114_x3 to prevent reads from F1x114 from generating NB
- * Array MCA errors. BKDG Doc #3116 Rev 1.07
- */
-
- { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
-
- { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0xFFFFFFFF }, /* Clear map */
-
- { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
-
- { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000000, 0xFFFFFFFF }, /* Clear map */
-
- /* Function 2 - DRAM Controller */
-
- /* Function 3 - Misc. Control */
- { 3, 0x40, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */
-
- { 3, 0x44, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1,
- [27] NbMcaToMstCpuEn = 1,
- [25] DisPciCfgCpuErrRsp = 1,
- [21] SyncOnAnyErrEn = 1,
- [20] SyncOnWDTEn = 1,
- [6] CpuErrDis = 1,
- [4] SyncPktPropDis = 1,
- [3] SyncPktGenDis = 1,
- [2] SyncOnUcEccEn = 1 */
-
- /* XBAR buffer settings */
- { 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
- 0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0,
- UpRspDBC = 0x1,
- DatBuf24 = 0x1,
- DnRspDBC = 0x1,
- DnReqDBC = 0x1,
- UpReqDBC = 0x2 */
-
- /* XBAR buffer settings */
- { 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL,
- 0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0,
- UpRspDBC = 0x2,
- DatBuf24 = 0x1,
- DnRspDBC = 0x1,
- DnReqDBC = 0x1,
- UpReqDBC = 0x2 */
-
- /* XBAR buffer settings */
- { 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1,
- UpRspDBC = 0x1,
- DnRspDBC = 0x1,
- DnReqDBC = 0x1,
- UpReqDBC = 0x2 */
-
- /* Errata 281 Workaround */
- { 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1),
- AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
-
- { 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x60018051, 0x700780F7 },
-
- { 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
- 0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0,
- IsocPreqCBC = 0x0,
- IsocReqCBC = 0x0,
- UpRspCBC = 0x4,
- DnPreqCBC = 0x1,
- UpPreqCBC = 0x1,
- DnRspCBC = 0x1,
- DnReqCBC = 0x1,
- UpReqCBC = 0x3 */
-
- { 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL,
- 0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0,
- IsocPreqCBC = 0x0,
- IsocReqCBC = 0x0,
- UpRspCBC = 0x5,
- DnPreqCBC = 0x1,
- UpPreqCBC = 0x1,
- DnRspCBC = 0x1,
- DnReqCBC = 0x1,
- UpReqCBC = 0x3 */
-
- { 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1,
- IsocPreqCBC = 0x0,
- IsocReqCBC = 0x1,
- UpRspCBC = 0x7,
- DnPreqCBC = 0x1,
- UpPreqCBC = 0x1,
- DnRspCBC = 0x1,
- DnReqCBC = 0x1,
- UpReqCBC = 0x5 */
-
- { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6,
- IsocPreqCBC = 0x1,
- IsocReqCBC = 0x2,
- UpRspCBC = 0x2,
- DnPreqCBC = 0x1,
- UpPreqCBC = 0x1,
- DnRspCBC = 0x1,
- DnReqCBC = 0x1,
- UpReqCBC = 0x1 */
-
- { 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA,
- 0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
- IsocPreqCBC = 0x0,
- IsocReqCBC = 0x0,
- ProbeCBC = 0x8,
- DnPreqCBC = 0x1,
- UpPreqCBC = 0x1,
- DnReqCBC = 0x1,
- UpReqCBC = 0x1 */
-
- { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0,
- IsocPreqCBC = 0x0,
- IsocReqCBC = 0x4,
- ProbeCBC = 0x8,
- DnPreqCBC = 0x0,
- UpPreqCBC = 0x1,
- DnReqCBC = 0x0,
- UpReqCBC = 0x1 */
-
- { 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
- IsocPreqCBC = 0x0,
- IsocReqCBC = 0x1,
- ProbeCBC = 0x7,
- DnPreqCBC = 0x2,
- UpPreqCBC = 0x1,
- DnReqCBC = 0x1,
- UpReqCBC = 0x1 */
-
- { 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
- 0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
- Sri2XbarFreeRspDBC = 0x0,
- Sri2XbarFreeXreqDBC = 0x9,
- Sri2XbarFreeRspCBC = 0x0,
- Sri2XbarFreeXreqCBC = 0x9,
- Xbar2SriFreeListCBC = 0x14 */
-
- { 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL,
- 0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
- Sri2XbarFreeRspDBC = 0x0,
- Sri2XbarFreeXreqDBC = 0x9,
- Sri2XbarFreeRspCBC = 0x0,
- Sri2XbarFreeXreqCBC = 0x9,
- Xbar2SriFreeListCBC = 0x14 */
-
- /* Errata 281 Workaround */
- { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
- AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
-
- { 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0,
- SrqExtFreeListBC = 0x8,
- Sri2XbarFreeRspDBC = 0x0,
- Sri2XbarFreeXreqDBC = 0xd,
- Sri2XbarFreeRspCBC = 0x0,
- Sri2XbarFreeXreqCBC = 0xf,
- Xbar2SriFreeListCBC = 0x16 */
-
- { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x00070814, 0x007FFF1F },
-
- { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00800756, 0x00F3FFFF },
-
- { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x00C37756, 0x00F3FFFF },
-
- { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x00000036, 0x000000FF },
-
- { 3, 0x140, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00a11755, 0x00f3ffff },
-
- /* Errata 281 Workaround */
- { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
- AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
- /* [3:0] RspTok = 0001b */
-
- { 3, 0x144, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000028, 0x000000ff },
-
- { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
- 0x8000052A, 0xD5FFFFFF },
-
- /* Core Interface Buffer Count */
- { 3, 0x1a0, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00034004, 0x00037007 }, /* CpuToNbFreeBufCnt = 0x3,
- L3ToSriReqCBC = 0x4,
- L3FreeListCBC = default,
- CpuCmdBufCnt = 0x4 */
-
- /* ACPI Power State Control Reg1 */
- { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0xE6002200, 0xFFFFFFFF },
-
- /* ACPI Power State Control Reg1 */
- { 3, 0x80, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0xe20be200, 0xefefef00 },
-
- /* ACPI Power State Control Reg2 */
- { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0xA0E641E6, 0xFFFFFFFF },
-
- /* ACPI Power State Control Reg2 */
- { 3, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x01e200e2, 0xefef00ef },
-
- { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
- 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
-
- { 3, 0xA0, AMD_DR_Bx, AMD_PTYPE_ALL,
- 0x00002800, 0x000003800 }, /* [13:11] PllLockTime = 5 */
-
- { 3, 0xA0, ((AMD_FAM10_ALL | AMD_FAM15_ALL) & ~(AMD_DR_Bx)), AMD_PTYPE_ALL,
- 0x00000800, 0x000003800 }, /* [13:11] PllLockTime = 1 */
-
- /* Reported Temp Control Register */
- { 3, 0xA4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */
-
- /* Clock Power/Timing Control 0 Register */
- { 3, 0xD4, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1,
- [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
-
- /* Clock Power/Timing Control 1 Register */
- { 3, 0xD8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x03000010, 0x0F000070 }, /* [6:4] VSRampTime = 1,
- * [27:24] ReConDel = 3 */
-
- /* Clock Power/Timing Control 1 Register */
- { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
- 0x00000006, 0x00000007 }, /* [2:0] VSSlamTime = 6 */
-
-
- /* Clock Power/Timing Control 2 Register */
- { 3, 0xDC, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */
-
-
- /* Extended NB MCA Config Register */
- { 3, 0x180, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7,
- [9] SyncOnUncNbAryEn = 1 ,
- [8] SyncOnProtEn = 1,
- [7] SyncFloodOnTgtAbtErr = 1,
- [6] SyncFloodOnDatErr = 1,
- [5] DisPciCfgCpuMstAbtRsp = 1,
- [1] SyncFloodOnUsPwDataErr = 1 */
-
- /* NB Configuration 2 */
- { 3, 0x188, AMD_DR_GT_B0, AMD_PTYPE_ALL,
- 0x00000010, 0x00000010 }, /* EnStpGntOnFlushMaskWakeup = 0x1 */
-
- /* NB Configuration 2 */
- { 3, 0x188, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000200, 0x00000200 }, /* DisL3HiPriFreeListAlloc = 0x1 */
-
- /* errata 346 - Fam10 C2, C3
- * System software should set F3x188[22] to 1b. */
- { 3, 0x188, AMD_DR_Cx, AMD_PTYPE_ALL,
- 0x00400000, 0x00400000 },
-
- /* L3 Control Register */
- { 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */
-
- /* Errata 504 workaround */
- { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00040000, 0x00040000 }, /* [18] = 1b */
-
- /* IBS Control Register */
- { 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
- 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */
-
- /* Erratum 619 - Family 15h Bx
- * System software should set F5x88[14] to 1b. */
- { 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL,
- 1 << 14, 1 << 14 },
-
- /* L3 Control 2 */
- { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL,
- 0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2,
- ImplRdAnySubUnavail = 0x1 */
-};
-
-
-/*
- * Default HyperTransport Phy and errata settings.
- */
-static const struct {
- u16 htreg; /* HT Phy Register index */
- uint64_t revision;
- u32 platform;
- u32 linktype;
- u32 data;
- u32 mask;
-} fam10_htphy_default[] = {
-
- /* Errata 344 - Fam10 C2/C3, D0/D1
- * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
- { 0x60, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x61, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x62, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x63, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x64, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x65, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x66, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x67, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x68, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
-
- { 0x70, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x71, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x72, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x73, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x74, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x75, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x76, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x77, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x78, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
-
- /* Errata 354 - Fam10 C2, C3
- * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
- { 0x40, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x41, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x42, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x43, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x44, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x45, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x46, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x47, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x48, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
-
- { 0x50, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x51, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x52, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x53, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x54, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x55, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x56, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x57, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
- { 0x58, AMD_DR_Cx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00000040, 0x00000040 },
-
- /* Errata 327 - Fam10 C2/C3, D0/D1
- * BIOS should set the Link Phy Impedance Register[RttCtl]
- * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
- * Link Phy Impedance Register[RttIndex]
- * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
- { 0xC0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x40040000, 0xe01F0000 },
- { 0xD0, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x40040000, 0xe01F0000 },
-
- { 0x520A,AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
-
- { 0x530A, AMD_DR_Cx | AMD_DR_Dx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
-
- { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
-
- { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
-
- { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
-
- { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
-
- { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
-
- { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
-
- /* Link Phy Receiver Loop Filter Registers */
- { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
- [21:14] LfcMin = 10h */
-
- { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
- [21:14] LfcMin = 10h */
-
- { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
- [21:14] LfcMin = 08h */
-
- { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
- [21:14] LfcMin = 08h */
-
- { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
- [20:16] RttIndex = 04h */
-
- { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
- P0XmtRdPtr = 0x2
- P1RcvRdPtr = 0xa
- P1XmtRdPtr = 0x0 */
-
- { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
- P0XmtRdPtr = 0x2
- P1RcvRdPtr = 0xa
- P1XmtRdPtr = 0x0 */
-
- { 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
- P0XmtRdPtr = 0x4
- P1RcvRdPtr = 0xd
- P1XmtRdPtr = 0x0 */
-
- { 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
- P0XmtRdPtr = 0x4
- P1RcvRdPtr = 0xd
- P1XmtRdPtr = 0x0 */
-
- /* Link Phy Receiver Loop Filter Registers */
- { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
- [21:14] LfcMin = 10h */
-
- { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
- [21:14] LfcMin = 10h */
-
- { 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
- [21:14] LfcMin = 08h */
-
- { 0xC1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
- 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
- [21:14] LfcMin = 08h */
-
- { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
- 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
- [20:16] RttIndex = 04h */
-
- { 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d,
- [7] DfeEn = 0x1 */
-
- { 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
- 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d,
- [7] DfeEn = 0x1 */
-};
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
deleted file mode 100644
index d4dec2b..0000000
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-/*
- * This file initializes the CPU cores for voltage and frequency settings
- * in the different power states.
- */
-/*
-
-checklist (functions are in this file if no source file named)
-Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
-
-2.4.2.6 Requirements for p-states
-
-1.- F3x[84:80] According to table 100 : prep_fid_change
-
-2.- COF/VID :
- 2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply
- fixPsNbVidBeforeWR(...)
- 2.4.2.9.1 Step 8 enable_fid_change
- We do this for all nodes, I don't understand BKDG 100% on
- whether this is or isn't meant by "on the local
- processor". Must be OK.
- 2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ?
- 2.4.2.9.1 Steps 11-12 init_fidvid_stage2
- 2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect,
- needs specific circuitry.
-
-3.- 2.4.2.7 dualPlaneOnly(dev)
-
-4.- 2.4.2.8 applyBoostFIDOffset(dev, nodeid)
-
-5.- enableNbPState1(dev)
-
-6.- 2.4.1.7
- a) UpdateSinglePlaneNbVid()
- b) setVSRamp(), called from prep_fid_change
- c) prep_fid_change
- d) improperly, for lack of voltage regulator details?,
- F3xA0[PsiVidEn] in defaults.h
- F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
-
-7.- TODO (Core Performance Boost is only available in revision E cpus, and we
- don't seem to support those yet, at least they don't have any
- constant in amddefs.h )
-
-8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required
- by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required
- if the warm reset is issued by coreboot to update NbFid. So it is required
- or not ? How can I tell who issued warm reset ?
- coreboot transitions to P0 instead, which is not recommended, and does
- not follow 2.4.2.15.2 to do so.
-
-9.- TODO Requires information on current delivery capability
- (depends on mainboard and maybe power supply ?). One might use a config
- option with the maximum number of Amperes that the board can deliver to CPU.
-
-10.- [Multiprocessor] TODO 2.4.2.12
- [Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
- but not sure this is what is meant by "Determine the valid set of
- P-states based on enabled P-states indicated
- in MSRC001_00[68:64][PstateEn]" in 2.4.2.6-10
-
-11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
-
-12.- generate ACPI for p-states.
- generated in powernow_acpi.c amd_generate_powernow()
-
-"must also be completed"
-
-a.- PllLockTime set in ruleset in defaults.h
- BKDG says set it "If MSRC001_00[68:64][CpuFid] is different between
- any two enabled P-states", but since it does not say "only if"
- I guess it is safe to do it always.
-
-b.- prep_fid_change(...)
-
- */
-
-#include <console/console.h>
-#include <cpu/amd/msr.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <northbridge/amd/amdht/AsPsDefs.h>
-#include <stdlib.h>
-
-static inline void print_debug_fv(const char *str, u32 val)
-{
-#if CONFIG(SET_FIDVID_DEBUG)
- printk(BIOS_DEBUG, "%s%x\n", str, val);
-#endif
-}
-
-static inline void print_debug_fv_8(const char *str, u8 val)
-{
-#if CONFIG(SET_FIDVID_DEBUG)
- printk(BIOS_DEBUG, "%s%02x\n", str, val);
-#endif
-}
-
-static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
-{
-#if CONFIG(SET_FIDVID_DEBUG)
- printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
-#endif
-}
-
-struct fidvid_st {
- u32 common_fid;
-};
-
-static void enable_fid_change(u8 fid)
-{
- u32 dword;
- u32 nodes;
- pci_devfn_t dev;
- int i;
-
- nodes = get_nodes();
-
- for (i = 0; i < nodes; i++) {
- dev = NODE_PCI(i, 3);
- dword = pci_read_config32(dev, 0xd4);
- dword &= ~0x1F;
- dword |= (u32) fid & 0x1F;
- dword |= 1 << 5; // enable
- pci_write_config32(dev, 0xd4, dword);
- printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x\n", i,
- dword);
- }
-}
-
-static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid)
-{
- // BKDG 2.4.2.8
- // Fam10h revision E only, but E is apparently not supported yet, therefore untested
- if ((cpuid_edx(0x80000007) & CPB_MASK)
- && ((cpuid_ecx(0x80000008) & NC_MASK) == 5) ) {
- u32 core = get_node_core_id_x().coreid;
- u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
- msr_t msr = rdmsr(PSTATE_0_MSR);
- u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
- cpuFid = cpuFid + asymetricBoostThisCore;
- msr.lo &= ~PS_CPU_FID_MASK;
- msr.lo |= cpuFid;
- wrmsr(PSTATE_0_MSR, msr);
- } else if (is_fam15h()) {
- uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c);
- uint8_t boost_count = (dword >> 2) & 0x7;
- if (boost_count > 0) {
- /* Enable boost */
- dword &= ~0x3;
- dword |= 0x1;
- pci_write_config32(NODE_PCI(nodeid, 4), 0x15c, dword);
- }
- }
-}
-
-static void enableNbPState1(pci_devfn_t dev)
-{
- uint64_t cpuRev = mctGetLogicalCPUID(0xFF);
- if (cpuRev & AMD_FAM10_C3) {
- u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK);
- if ( nbPState){
- u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
- u32 i;
- for (i = nbPState; i < NM_PS_REG; i++) {
- msr_t msr = rdmsr(PSTATE_0_MSR + i);
- if (msr.hi & PS_EN_MASK ) {
- msr.hi |= NB_DID_M_ON;
- msr.lo &= NB_VID_MASK_OFF;
- msr.lo |= ( nbVid1 << NB_VID_POS);
- wrmsr(PSTATE_0_MSR + i, msr);
- }
- }
- }
- }
-}
-
-static u8 setPStateMaxVal(pci_devfn_t dev)
-{
- u8 i, maxpstate=0;
- for (i = 0; i < NM_PS_REG; i++) {
- msr_t msr = rdmsr(PSTATE_0_MSR + i);
- if (msr.hi & PS_IDD_VALUE_MASK) {
- msr.hi |= PS_EN_MASK;
- wrmsr(PSTATE_0_MSR + i, msr);
- }
- if (msr.hi & PS_EN_MASK) {
- maxpstate = i;
- }
- }
- //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
- u32 reg = pci_read_config32(dev, CPTC2);
- reg &= PS_MAX_VAL_MASK;
- reg |= (maxpstate << PS_MAX_VAL_POS);
- pci_write_config32(dev, CPTC2,reg);
- return maxpstate;
-}
-
-static void dualPlaneOnly(pci_devfn_t dev)
-{
- // BKDG 2.4.2.7
-
- uint64_t cpuRev = mctGetLogicalCPUID(0xFF);
- if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2)
- && (cpuRev & (AMD_DR_Cx | AMD_DR_Ex))) {
- if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK)
- && (pci_read_config32(dev, 0xA0) & PVI_MODE)) {
- if (cpuid_edx(CPUID_EXT_PM) & CPB_MASK) {
- // revision E only, but E is apparently not supported yet, therefore untested
- msr_t minPstate = rdmsr(PSTATE_1_MSR);
- wrmsr(PSTATE_1_MSR, rdmsr(PSTATE_4_MSR));
- wrmsr(PSTATE_4_MSR, minPstate);
- } else {
- msr_t msr;
- msr.lo=0; msr.hi=0;
- wrmsr(PSTATE_0_MSR, rdmsr(PSTATE_4_MSR));
- wrmsr(PSTATE_4_MSR, msr);
- }
-
- //FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
- u8 maxpstate = setPStateMaxVal(dev);
-
- u32 reg = pci_read_config32(dev, HTC_REG);
- reg &= HTC_PS_LMT_MASK;
- reg |= (maxpstate << PS_LIMIT_POS);
- pci_write_config32(dev, HTC_REG,reg);
- }
- }
-}
-
-static int vidTo100uV(u8 vid)
-{
- // returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV
- // BKDG #31116 rev 3.48 2.4.1.6
- int voltage;
- if (vid >= 0x7c) {
- voltage = 0;
- } else {
- voltage = (15500 - (125*vid));
- }
- return voltage;
-}
-
-static void setVSRamp(pci_devfn_t dev)
-{
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
- * If this field accepts 8 values between 10 and 500 us why
- * does page 324 say "BIOS should set this field to 001b."
- * (20 us) ?
- * Shouldn't it depend on the voltage regulators, mainboard
- * or something ?
- */
- u32 dword;
- dword = pci_read_config32(dev, 0xd8);
- dword &= VSRAMP_MASK;
- dword |= VSRAMP_VALUE;
- pci_write_config32(dev, 0xd8, dword);
-}
-
-static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev)
-{
- u8 pviModeFlag;
- u8 highVoltageVid, lowVoltageVid, bValue;
- u16 minimumSlamTime;
- u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */
- u32 dtemp;
- msr_t msr;
-
- /* This function calculates the VsSlamTime using the range of possible
- * voltages instead of a hardcoded 200us.
- * Note: his function is called only from prep_fid_change,
- * and that from init_cpus.c finalize_node_setup()
- * (after set AMD MSRs and init ht )
- */
-
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
- /* Calculate Slam Time
- * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV
- * In our case, we will scale the values by 100 to avoid
- * decimals.
- */
-
- /* Determine if this is a PVI or SVI system */
- if (is_fam15h()) {
- pviModeFlag = 0;
- } else {
- dtemp = pci_read_config32(dev, 0xa0);
-
- if (dtemp & PVI_MODE)
- pviModeFlag = 1;
- else
- pviModeFlag = 0;
- }
-
- /* Get P0's voltage */
- /* MSRC001_00[68:64] are not programmed yet when called from
- prep_fid_change, one might use F4x1[F0:E0] instead, but
- theoretically MSRC001_00[68:64] are equal to them after
- reset. */
- msr = rdmsr(PSTATE_0_MSR);
- highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
- if (!(msr.hi & 0x80000000)) {
- printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
- highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0)
- >> PS_CPU_VID_SHFT) & 0x7F);
- }
-
- /* If SVI, we only care about CPU VID.
- * If PVI, determine the higher voltage b/t NB and CPU
- */
- if (pviModeFlag) {
- bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
- if (highVoltageVid > bValue)
- highVoltageVid = bValue;
- }
-
- /* Get PSmax's index */
- msr = rdmsr(PS_LIM_REG);
- bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
-
- /* Get PSmax's VID */
- msr = rdmsr(PSTATE_0_MSR + bValue);
- lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
- if (!(msr.hi & 0x80000000)) {
- printk(BIOS_ERR, "P-state info in MSR%8x is invalid !!!\n",
- PSTATE_0_MSR + bValue);
- lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4))
- >> PS_CPU_VID_SHFT) & 0x7F);
- }
-
- /* If SVI, we only care about CPU VID.
- * If PVI, determine the higher voltage b/t NB and CPU
- * BKDG 2.4.1.7 (a)
- */
- if (pviModeFlag) {
- bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
- if (lowVoltageVid > bValue)
- lowVoltageVid = bValue;
- }
-
- /* Get AltVID */
- dtemp = pci_read_config32(dev, 0xdc);
- bValue = (u8) (dtemp & BIT_MASK_7);
-
- /* Use the VID with the lowest voltage (higher VID) */
- if (lowVoltageVid < bValue)
- lowVoltageVid = bValue;
-
- u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB;
- minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */
-
-
- /* Now round up to nearest register setting.
- * Note that if we don't find a value, we
- * will fall through to a value of 7
- */
- for (bValue = 0; bValue < 7; bValue++) {
- if (minimumSlamTime <= vSlamTimes[bValue])
- break;
- }
-
- /* Apply the value */
- dtemp = pci_read_config32(dev, 0xD8);
- dtemp &= VSSLAM_MASK;
- dtemp |= bValue;
- pci_write_config32(dev, 0xd8, dtemp);
-}
-
-static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {
- uint8_t link0isGen3 = 0;
- uint8_t offset;
- if (AMD_CpuFindCapability(node, 0, &offset)) {
- link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3 );
- }
- /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
- S1g3 in link Gen3 mode, but I don't know how to tell
- package S1g3 from S1g4 */
- if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
- && link0isGen3) {
- return 5; /* divide clk by 128*/
- } else {
- return 4; /* divide clk by 16 */
- }
-}
-
-
-static u32 power_up_down(int node, u8 procPkg) {
- uint32_t dword=0;
- /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
- u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
- || (procPkg == AMD_PKGTYPE_S1gX)
- || (procPkg == AMD_PKGTYPE_ASB2));
-
- if (singleLinkFlag) {
- /*
- * PowerStepUp=01000b - 50nS
- * PowerStepDown=01000b - 50ns
- */
- dword |= PW_STP_UP50 | PW_STP_DN50;
- } else {
- uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
- uint32_t isocEn = 0;
- int j;
- for (j=0; (j<4) && (!isocEn); j++ ) {
- u8 offset;
- if (AMD_CpuFindCapability(node, j, &offset)) {
- isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
- }
- }
-
- if (is_fam15h()) {
- /* Family 15h always uses 100ns for multilink processors */
- dword |= PW_STP_UP100 | PW_STP_DN100;
- } else if (dispRefModeEn || isocEn) {
- dword |= PW_STP_UP50 | PW_STP_DN50;
- } else {
- /* get number of cores for PowerStepUp & PowerStepDown in server
- * 1 core - 400nS - 0000b
- * 2 cores - 200nS - 0010b
- * 3 cores - 133nS -> 100nS - 0011b
- * 4 cores - 100nS - 0011b
- */
- switch (get_core_num_in_bsp(node)) {
- case 0:
- dword |= PW_STP_UP400 | PW_STP_DN400;
- break;
- case 1:
- case 2:
- dword |= PW_STP_UP200 | PW_STP_DN200;
- break;
- case 3:
- dword |= PW_STP_UP100 | PW_STP_DN100;
- break;
- default:
- dword |= PW_STP_UP100 | PW_STP_DN100;
- break;
- }
- }
- }
-
- return dword;
-}
-
-static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {
-
- pci_devfn_t dev = NODE_PCI(node, 3);
-
- /* Program fields in Clock Power/Control register0 (F3xD4) */
-
- /* set F3xD4 Clock Power/Timing Control 0 Register
- * NbClkDidApplyAll=1b
- * NbClkDid=100b or 101b
- * PowerStepUp= "platform dependent"
- * PowerStepDown= "platform dependent"
- * LinkPllLink=01b
- * ClkRampHystCtl=HW default
- * ClkRampHystSel=1111b
- */
- uint32_t dword= pci_read_config32(dev, 0xd4);
- dword &= CPTC0_MASK;
- dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
- dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT);
-
- dword |= power_up_down(node, procPkg);
-
- pci_write_config32(dev, 0xd4, dword);
-
-}
-
-static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
- uint8_t procPkg)
-{
- /* check PVI/SVI */
- uint32_t dword = pci_read_config32(dev, 0xa0);
-
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
- /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
- if (dword & PVI_MODE) { /* PVI */
- /* set slamVidMode to 0 for PVI */
- dword &= VID_SLAM_OFF;
- } else { /* SVI */
- /* set slamVidMode to 1 for SVI */
- dword |= VID_SLAM_ON;
- }
- /* set the rest of A0 since we're at it... */
-
- if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
- dword |= NB_PSTATE_FORCE_ON;
- } // else should we clear it ?
-
-
- if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
- dword |= BP_INS_TRI_EN_ON;
- }
-
- /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
- #if 0
- if (cpuRev & AMD_FAM10_C3) {
- dword |= SVI_HIGH_FREQ_ON;
- }
- #endif
- pci_write_config32(dev, 0xa0, dword);
-}
-
-static void config_nb_syn_ptr_adj(pci_devfn_t dev, uint64_t cpuRev)
-{
- /* Note the following settings are additional from the ported
- * function setFidVidRegs()
- */
- /* adjust FIFO between nb and core clocks to max allowed
- values (min latency) */
- uint32_t nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;
- uint8_t nbSynPtrAdj;
- if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL) )
- || ((cpuRev & AMD_RB_C3) && (nbPstate != 0))) {
- nbSynPtrAdj = 5;
- } else {
- nbSynPtrAdj = 6;
- }
-
- uint32_t dword = pci_read_config32(dev, 0xdc);
- dword &= ~NB_SYN_PTR_ADJ_MASK;
- dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS;
- /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
- pci_write_config32(dev, 0xdc, dword);
-}
-
-static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
- uint8_t procPkg)
-{
- if (is_fam15h()) {
- /* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
- pci_write_config32(dev, 0x80, 0xe20be281);
-
- /* Family 15h BKDG Rev. 3.14 D18F3x84 recommended settings */
- pci_write_config32(dev, 0x84, 0x01e200e2);
- } else {
- /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
- uint32_t dword;
- uint32_t c1= 1;
- if (cpuRev & (AMD_DR_Bx)) {
- // will coreboot ever enable cache scrubbing ?
- // if it does, will it be enough to check the current state
- // or should we configure for what we'll set up later ?
- dword = pci_read_config32(dev, 0x58);
- uint32_t scrubbingCache = dword &
- ( (0x1F << 16) // DCacheScrub
- | (0x1F << 8) ); // L2Scrub
- if (scrubbingCache) {
- c1 = 0x80;
- } else {
- c1 = 0xA0;
- }
- } else { // rev C or later
- // same doubt as cache scrubbing: ok to check current state ?
- dword = pci_read_config32(dev, 0xdc);
- uint32_t cacheFlushOnHalt = dword & (7 << 16);
- if (!cacheFlushOnHalt) {
- c1 = 0x80;
- }
- }
- dword = (c1 << 24) | (0xE641E6);
- pci_write_config32(dev, 0x84, dword);
-
- /* FIXME: BKDG Table 100 says if the link is at a Gen1
- * frequency and the chipset does not support a 10us minimum LDTSTOP
- * assertion time, then { If ASB2 && SVI then smaf001 = F6h else
- * smaf001=87h. } else ... I hardly know what it means or how to check
- * it from here, so I bluntly assume it is false and code here the else,
- * which is easier
- */
-
- uint32_t smaf001 = 0xE6;
- if (cpuRev & AMD_DR_Bx ) {
- smaf001 = 0xA6;
- } else {
- #if 0
- if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
- smaf001 = 0xF6;
- }
- #endif
- }
- uint32_t fidvidChange = 0;
- if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))
- || (cpuRev & AMD_RB_C3) ) {
- fidvidChange=0x0B;
- }
- dword = (0xE6 << 24) | (fidvidChange << 16)
- | (smaf001 << 8) | 0x81;
- pci_write_config32(dev, 0x80, dword);
- }
-}
-
-void prep_fid_change(void)
-{
- u32 dword;
- u32 nodes;
- pci_devfn_t dev;
- int i;
-
- /* This needs to be run before any Pstate changes are requested */
-
- nodes = get_nodes();
-
- for (i = 0; i < nodes; i++) {
- printk(BIOS_DEBUG, "Prep FID/VID Node:%02x\n", i);
- dev = NODE_PCI(i, 3);
- uint64_t cpuRev = mctGetLogicalCPUID(0xFF);
- u8 procPkg = mctGetProcessorPackageType();
-
- setVSRamp(dev);
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
- /* Figure out the value for VsSlamTime and program it */
- recalculateVsSlamTimeSettingOnCorePre(dev);
-
- config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
-
- config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
- config_nb_syn_ptr_adj(dev,cpuRev);
-
- config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
-
- dword = pci_read_config32(dev, 0x80);
- printk(BIOS_DEBUG, " F3x80: %08x\n", dword);
- dword = pci_read_config32(dev, 0x84);
- printk(BIOS_DEBUG, " F3x84: %08x\n", dword);
- dword = pci_read_config32(dev, 0xd4);
- printk(BIOS_DEBUG, " F3xD4: %08x\n", dword);
- dword = pci_read_config32(dev, 0xd8);
- printk(BIOS_DEBUG, " F3xD8: %08x\n", dword);
- dword = pci_read_config32(dev, 0xdc);
- printk(BIOS_DEBUG, " F3xDC: %08x\n", dword);
- }
-}
-
-static void waitCurrentPstate(u32 target_pstate) {
- msr_t initial_msr = rdmsr(TSC_MSR);
- msr_t pstate_msr = rdmsr(PS_STS_REG);
- msr_t tsc_msr;
- u8 timedout;
-
- /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a
- * P1 that is a copy of P0, therefore has the same NB DID but the
- * TSC will count twice per tick, so we have to wait for twice the
- * count to achieve the desired timeout. But I'm likely to
- * misunderstand this...
- */
- u32 corrected_timeout = ((pstate_msr.lo==1)
- && (!(rdmsr(PSTATE_1_MSR).lo & NB_DID_M_ON))) ?
- WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;
- msr_t timeout;
-
- timeout.lo = initial_msr.lo + corrected_timeout;
- timeout.hi = initial_msr.hi;
- if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) {
- timeout.hi++;
- }
-
- // assuming TSC ticks at 1.25 ns per tick (800 MHz)
- do {
- pstate_msr = rdmsr(PS_STS_REG);
- tsc_msr = rdmsr(TSC_MSR);
- timedout = (tsc_msr.hi > timeout.hi)
- || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
- } while ( (pstate_msr.lo != target_pstate) && (! timedout) );
-
- if (pstate_msr.lo != target_pstate) {
- msr_t limit_msr = rdmsr(PS_LIM_REG);
- printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n",
- cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo);
-
- do { // should we just go on instead ?
- pstate_msr = rdmsr(PS_STS_REG);
- } while (pstate_msr.lo != target_pstate);
- }
-}
-
-static void set_pstate(u32 nonBoostedPState) {
- msr_t msr;
- uint8_t skip_wait;
-
- // Transition P0 for calling core.
- msr = rdmsr(PS_CTL_REG);
-
- msr.lo = nonBoostedPState;
- wrmsr(PS_CTL_REG, msr);
-
- if (is_fam15h()) {
- /* Do not wait for the first (even) set of cores to transition on Family 15h systems */
- if ((cpuid_ebx(0x00000001) & 0x01000000))
- skip_wait = 0;
- else
- skip_wait = 1;
- } else {
- skip_wait = 0;
- }
-
- if (!skip_wait) {
- /* Wait for core to transition to P0 */
- waitCurrentPstate(nonBoostedPState);
- }
-}
-
-static void UpdateSinglePlaneNbVid(void)
-{
- u32 nbVid, cpuVid;
- u8 i;
- msr_t msr;
-
- /* copy higher voltage (lower VID) of NBVID & CPUVID to both */
- for (i = 0; i < 5; i++) {
- msr = rdmsr(PSTATE_0_MSR + i);
- nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
- cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
-
- if (nbVid != cpuVid) {
- if (nbVid > cpuVid)
- nbVid = cpuVid;
-
- msr.lo = msr.lo & PS_BOTH_VID_OFF;
- msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
- msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
- wrmsr(PSTATE_0_MSR + i, msr);
- }
- }
-}
-
-static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
-{
- msr_t msr;
- u8 startup_pstate;
-
- /* This function sets NbVid before the warm reset.
- * Get StartupPstate from MSRC001_0071.
- * Read Pstate register pointed by [StartupPstate].
- * and copy its content to P0 and P1 registers.
- * Copy newNbVid to P0[NbVid].
- * transition to P1 on all cores,
- * then transition to P0 on core 0.
- * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
- * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration
- * for SVI and Single-Plane PVI Systems
- */
-
- msr = rdmsr(MSR_COFVID_STS);
- startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
-
- /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for
- * this node in P0. Then transition to P1 for corex and P0
- * for core0. These setting will be cleared by the warm reset
- */
- msr = rdmsr(PSTATE_0_MSR + startup_pstate);
- wrmsr(PSTATE_1_MSR, msr);
- wrmsr(PSTATE_0_MSR, msr);
-
- /* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
- * max(1,F3xDC[PstateMaxVal] ) because it would take
- * synchronization between cores and we don't think
- * PstatMaxVal is going to be 0 on cold reset anyway ?
- */
- if (!(pci_read_config32(dev, 0xdc) & (~PS_MAX_VAL_MASK))) {
- printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n");
- };
-
- msr.lo &= ~0xFE000000; // clear nbvid
- msr.lo |= (newNbVid << 25);
- wrmsr(PSTATE_0_MSR, msr);
-
- if (pviMode) { /* single plane*/
- UpdateSinglePlaneNbVid();
- }
-
- // Transition to P1 for all APs and P0 for core0.
- set_pstate(1);
-
- if (coreid == 0) {
- set_pstate(0);
- }
-
- /* missing step 7 (restore PstateMax to 0 if needed) because
- * we skipped step 2
- */
-
-}
-
-static u32 needs_NB_COF_VID_update(void)
-{
- u8 nb_cof_vid_update;
- u8 nodes;
- u8 i;
-
- if (is_fam15h())
- return 0;
-
- /* If any node has nb_cof_vid_update set all nodes need an update. */
- nodes = get_nodes();
- nb_cof_vid_update = 0;
- for (i = 0; i < nodes; i++) {
- uint64_t cpuRev = mctGetLogicalCPUID(i);
- u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D));
- if (nbCofVidUpdateDefined
- && (pci_read_config32(NODE_PCI(i, 3), 0x1FC)
- & NB_COF_VID_UPDATE_MASK)) {
- nb_cof_vid_update = 1;
- break;
- }
- }
- return nb_cof_vid_update;
-}
-
-static u32 init_fidvid_core(u32 nodeid, u32 coreid)
-{
- pci_devfn_t dev;
- u32 vid_max;
- u32 fid_max = 0;
- u8 nb_cof_vid_update = needs_NB_COF_VID_update();
- u8 pvimode;
- u32 reg1fc;
-
- /* Steps 1-6 of BIOS NB COF and VID Configuration
- * for SVI and Single-Plane PVI Systems. BKDG 2.4.2.9 #31116 rev 3.48
- */
- dev = NODE_PCI(nodeid, 3);
- if (is_fam15h())
- pvimode = 0;
- else
- pvimode = pci_read_config32(dev, PW_CTL_MISC) & PVI_MODE;
- reg1fc = pci_read_config32(dev, 0x1FC);
-
- if (nb_cof_vid_update) {
- vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT;
- fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT;
-
- if (!pvimode) { /* SVI, dual power plane */
- vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT );
- fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT );
- }
- /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
- fixPsNbVidBeforeWR(vid_max, coreid, dev, pvimode);
-
- /* fid setup is handled by the BSP at the end. */
-
- } else { /* ! nb_cof_vid_update */
- /* Use max values */
- if (pvimode)
- UpdateSinglePlaneNbVid();
- }
-
- return ((nb_cof_vid_update << 16) | (fid_max << 8));
-
-}
-
-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
-{
- u32 send;
-
- printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
-
- send = init_fidvid_core(nodeid, coreid);
- send |= (apicid << 24); // ap apicid
-
- // Send signal to BSP about this AP max fid
- // This also indicates this AP is ready for warm reset (if required).
- lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET);
-}
-
-static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
-{
- u32 fidmax;
- u32 fidmax_new;
-
- fidmax = (fid_packed >> 8) & 0xFF;
-
- fidmax_new = (fid_packed_new >> 8) & 0xFF;
-
- if (fidmax > fidmax_new) {
- fidmax = fidmax_new;
- }
-
- fid_packed &= 0xFF << 16;
- fid_packed |= (fidmax << 8);
- fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
-
- return fid_packed;
-}
-
-static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
-{
- u32 readback = 0;
- u32 timeout = 1;
-
- struct fidvid_st *fvp = gp;
- int loop;
-
- print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
-
- loop = 100000;
- while (--loop > 0) {
- if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
- continue;
- if (((readback & 0x3f) == F10_APSTATE_RESET)
- || (is_fam15h() && ((readback & 0x3f) == F10_APSTATE_ASLEEP))) {
- timeout = 0;
- break; /* target ap is in stage 1 */
- }
- }
-
- if (timeout) {
- printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
- __func__, ap_apicid);
- return;
- }
-
- print_debug_fv("\treadback = ", readback);
-
- fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
-
- print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
-
-}
-
-static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
-{
- msr_t msr;
- u8 i;
- u8 StartupPstate;
-
- /* BKDG 2.4.2.9.1 11-12
- * This function copies newNbVid to NbVid bits in P-state
- * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of
- * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in
- * P-state Registers[4:0] if its IddValue!=0 in case of
- * NbVidUpdatedAll=1. Then transition to StartPstate.
- */
-
- /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
- for (i = 0; i < 5; i++) {
- msr = rdmsr(PSTATE_0_MSR + i);
- /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
- if ( (msr.hi & PS_IDD_VALUE_MASK)
- && (msr.hi & PS_EN_MASK)
- &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {
- msr.lo &= PS_NB_VID_M_OFF;
- msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT;
- wrmsr(PSTATE_0_MSR + i, msr);
- }
- }
-
- /* Not documented. Would overwrite Nb_Vids just copied
- * should we just update cpu_vid or nothing at all ?
- */
- if (pviMode) { //single plane
- UpdateSinglePlaneNbVid();
- }
- /* For each core in the system, transition all cores to StartupPstate */
- msr = rdmsr(MSR_COFVID_STS);
- StartupPstate = msr.hi & 0x07;
-
- /* Set and wait for StartupPstate to set. */
- set_pstate(StartupPstate);
-
-}
-
-static void finalPstateChange(void)
-{
- /* Enable P0 on all cores for best performance.
- * Linux can slow them down later if need be.
- * It is safe since they will be in C1 halt
- * most of the time anyway.
- */
- set_pstate(0);
-}
-
-void init_fidvid_stage2(u32 apicid, u32 nodeid)
-{
- msr_t msr;
- pci_devfn_t dev;
- u32 reg1fc;
- u32 dtemp;
- u32 nbvid;
- u8 nb_cof_vid_update = needs_NB_COF_VID_update();
- u8 NbVidUpdateAll;
- u8 pvimode;
-
- /* After warm reset finish the fid/vid setup for all cores. */
-
- /* If any node has nb_cof_vid_update set all nodes need an update. */
-
- dev = NODE_PCI(nodeid, 3);
- if (is_fam15h())
- pvimode = 0;
- else
- pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
- reg1fc = pci_read_config32(dev, 0x1FC);
- nbvid = (reg1fc >> 7) & 0x7F;
- NbVidUpdateAll = (reg1fc >> 1) & 1;
-
- if (nb_cof_vid_update) {
- if (!pvimode) { /* SVI */
- nbvid = nbvid - ((reg1fc >> 17) & 0x1F);
- }
- /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
- fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode);
- } else { /* !nb_cof_vid_update */
- if (pvimode)
- UpdateSinglePlaneNbVid();
- }
- dtemp = pci_read_config32(dev, 0xA0);
- dtemp &= PLLLOCK_OFF;
- dtemp |= PLLLOCK_DFT_L;
- pci_write_config32(dev, 0xA0, dtemp);
-
- dualPlaneOnly(dev);
- applyBoostFIDOffset(dev, nodeid);
- enableNbPState1(dev);
-
- finalPstateChange();
-
- if (!is_fam15h()) {
- /* Set TSC to tick at the P0 ndfid rate */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= 1 << 24;
- wrmsr(HWCR_MSR, msr);
- }
-}
-
-
-#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
-struct ap_apicid_st {
- u32 num;
- // it could use 256 bytes for 64 node quad core system
- u8 apicid[NODE_NUMS * 4];
-};
-
-static void store_ap_apicid(unsigned int ap_apicid, void *gp)
-{
- struct ap_apicid_st *p = gp;
-
- p->apicid[p->num++] = ap_apicid;
-
-}
-#endif
-
-
-int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
-{
-#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
- struct ap_apicid_st ap_apicidx;
- u32 i;
-#endif
- struct fidvid_st fv;
-
- printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
-
- /* Steps 1-6 of BIOS NB COF and VID Configuration
- * for SVI and Single-Plane PVI Systems.
- */
- fv.common_fid = init_fidvid_core(0, 0);
-
- print_debug_fv("BSP fid = ", fv.common_fid);
-
-#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
- !CONFIG(SET_FIDVID_CORE0_ONLY)
- /* For all APs (We know the APIC ID of all APs even when the APIC ID
- is lifted) remote read from AP LAPIC_MSG_REG about max fid.
- Then calculate the common max fid that can be used for all
- APs and BSP */
- ap_apicidx.num = 0;
-
- for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, -1, store_ap_apicid, &ap_apicidx);
-
- for (i = 0; i < ap_apicidx.num; i++) {
- init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
- }
-#else
- for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv);
-#endif
-
- print_debug_fv("common_fid = ", fv.common_fid);
-
- if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */
-
- // Enable the common fid and other settings.
- enable_fid_change((fv.common_fid >> 8) & 0x1F);
-
- // nbfid change need warm reset, so reset at first
- return 1;
- }
-
- return 0; // No FID/VID changes. Don't reset
-}
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
deleted file mode 100644
index ae04f2a..0000000
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ /dev/null
@@ -1,1849 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/amd/msr.h>
-#include <device/pci_ops.h>
-#include <types.h>
-
-#include "init_cpus.h"
-
-#if CONFIG(HAVE_OPTION_TABLE)
-#include "option_table.h"
-#endif
-#include <pc80/mc146818rtc.h>
-
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <northbridge/amd/amdht/AsPsDefs.h>
-#include <northbridge/amd/amdht/porting.h>
-#include <northbridge/amd/amdht/h3ncmn.h>
-
-#include <southbridge/amd/common/reset.h>
-
-#include "cpu/amd/car/disable_cache_as_ram.c"
-
-#if CONFIG(PCI_IO_CFG_EXT)
-static void set_EnableCf8ExtCfg(void)
-{
- // set the NB_CFG_MSR[46]=1;
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
- msr.hi |= (1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-}
-#else
-static void set_EnableCf8ExtCfg(void) { }
-#endif
-
-// #define DEBUG_HT_SETUP 1
-// #define FAM10_AP_NODE_SEQUENTIAL_START 1
-
-uint32_t get_boot_apic_id(uint8_t node, uint32_t core) {
- uint32_t ap_apicid;
-
- uint32_t nb_cfg_54;
- uint32_t siblings;
- uint32_t cores_found;
-
- uint8_t fam15h = 0;
- uint8_t rev_gte_d = 0;
- uint8_t dual_node = 0;
- uint32_t f3xe8;
- uint32_t family;
- uint32_t model;
-
- uint32_t ApicIdCoreIdSize;
-
- /* Assume that all node are same stepping, otherwise we can use use
- nb_cfg_54 from bsp for all nodes */
- nb_cfg_54 = read_nb_cfg_54();
- f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
-
- family = model = cpuid_eax(0x80000001);
- model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f) {
- /* Family 15h or later */
- fam15h = 1;
- nb_cfg_54 = 1;
- }
-
- if ((model >= 0x8) || fam15h)
- /* Revision D or later */
- rev_gte_d = 1;
-
- if (rev_gte_d)
- /* Check for dual node capability */
- if (f3xe8 & 0x20000000)
- dual_node = 1;
-
- ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
- if (ApicIdCoreIdSize) {
- siblings = ((1 << ApicIdCoreIdSize) - 1);
- } else {
- siblings = 3; //quad core
- }
-
- cores_found = get_core_num_in_bsp(node);
- if (siblings > cores_found)
- siblings = cores_found;
-
- if (dual_node) {
- ap_apicid = 0;
- if (fam15h) {
- ap_apicid |= ((node >> 1) & 0x3) << 5; /* Node ID */
- ap_apicid |= ((node & 0x1) * (siblings + 1)) + core; /* Core ID */
- } else {
- if (nb_cfg_54) {
- ap_apicid |= ((node >> 1) & 0x3) << 4; /* Node ID */
- ap_apicid |= ((node & 0x1) * (siblings + 1)) + core; /* Core ID */
- } else {
- ap_apicid |= node & 0x3; /* Node ID */
- ap_apicid |= (((node & 0x1) * (siblings + 1)) + core) << 4; /* Core ID */
- }
- }
- } else {
- if (fam15h) {
- ap_apicid = 0;
- ap_apicid |= (node & 0x7) << 4; /* Node ID */
- ap_apicid |= core & 0xf; /* Core ID */
- } else {
- ap_apicid = node * (nb_cfg_54 ? (siblings + 1) : 1) +
- core * (nb_cfg_54 ? 1 : 64);
- }
- }
-
- printk(BIOS_DEBUG, "%s: using %d as APIC ID for node %d, core %d\n", __func__, ap_apicid, node, core);
-
- return ap_apicid;
-}
-
-//core_range = 0 : all cores
-//core range = 1 : core 0 only
-//core range = 2 : cores other than core0
-
-static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
- process_ap_t process_ap, void *gp)
-{
- // here assume the OS don't change our apicid
- u32 ap_apicid;
-
- u32 nodes;
- u32 disable_siblings;
- u32 cores_found;
- int i, j;
-
- /* get_nodes define in ht_wrapper.c */
- nodes = get_nodes();
-
- if (!CONFIG(LOGICAL_CPUS) ||
- read_option(multi_core, 0) != 0) { // 0 means multi core
- disable_siblings = 1;
- } else {
- disable_siblings = 0;
- }
-
- for (i = 0; i < nodes; i++) {
- if ((node >= 0) && (i != node))
- continue;
-
- cores_found = get_core_num_in_bsp(i);
-
- u32 jstart, jend;
-
- if (core_range == 2) {
- jstart = 1;
- } else {
- jstart = 0;
- }
-
- if (disable_siblings || (core_range == 1)) {
- jend = 0;
- } else {
- jend = cores_found;
- }
-
- for (j = jstart; j <= jend; j++) {
- ap_apicid = get_boot_apic_id(i, j);
-
-#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
-#if !CONFIG(LIFT_BSP_APIC_ID)
- if ((i != 0) || (j != 0)) /* except bsp */
-#endif
- ap_apicid += CONFIG_APIC_ID_OFFSET;
-#endif
-
- if (ap_apicid == bsp_apicid)
- continue;
-
- process_ap(ap_apicid, gp);
-
- }
- }
-}
-
-static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
-{
- int timeout;
- u32 status;
- int result;
- lapic_wait_icr_idle();
- lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
- lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
-
-/* Extra busy check compared to lapic.h */
- timeout = 0;
- do {
- status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
- } while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
-
- timeout = 0;
- do {
- status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
- } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
-
- result = -1;
-
- if (status == LAPIC_ICR_RR_VALID) {
- *pvalue = lapic_read(LAPIC_RRR);
- result = 0;
- }
- return result;
-}
-
-#if CONFIG(SET_FIDVID)
-static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
-#endif
-
-static __always_inline
-void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id,
- const char *str)
-{
- printk(BIOS_DEBUG,
- "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str,
- apicid, id.nodeid, id.coreid);
-}
-
-uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2)
-{
- u32 readback = 0;
- u32 timeout = 1;
- int loop = 4000000;
- while (--loop > 0) {
- if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0)
- continue;
- if ((readback & 0x3f) == state || (readback & 0x3f) == state2 || (readback & 0x3f) == F10_APSTATE_RESET) {
- timeout = 0;
- break; //target CPU is in stage started
- }
- }
- if (timeout) {
- if (readback) {
- timeout = readback;
- }
- }
-
- return timeout;
-}
-
-static void wait_ap_started(u32 ap_apicid, void *gp)
-{
- u32 timeout;
- timeout = wait_cpu_state(ap_apicid, F10_APSTATE_STARTED, F10_APSTATE_ASLEEP);
- printk(BIOS_DEBUG, "* AP %02x", ap_apicid);
- if (timeout) {
- printk(BIOS_DEBUG, " timed out:%08x\n", timeout);
- } else {
- printk(BIOS_DEBUG, "started\n");
- }
-}
-
-void wait_all_other_cores_started(u32 bsp_apicid)
-{
- // all aps other than core0
- printk(BIOS_DEBUG, "started ap apicid: ");
- for_each_ap(bsp_apicid, 2, -1, wait_ap_started, (void *)0);
- printk(BIOS_DEBUG, "\n");
-}
-
-void allow_all_aps_stop(u32 bsp_apicid)
-{
- /* Called by the BSP to indicate AP can stop */
-
- /* FIXME Do APs use this? */
-
- // allow aps to stop use 6 bits for state
- lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED);
-}
-
-static void wait_ap_stopped(u32 ap_apicid, void *gp)
-{
- u32 timeout;
- timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP);
- printk(BIOS_DEBUG, "* AP %02x", ap_apicid);
- if (timeout) {
- printk(BIOS_DEBUG, " timed out:%08x\n", timeout);
- } else {
- printk(BIOS_DEBUG, "stopped\n");
- }
-}
-
-void wait_all_other_cores_stopped(u32 bsp_apicid)
-{
- // all aps other than core0
- printk(BIOS_DEBUG, "stopped ap apicid: ");
- for_each_ap(bsp_apicid, 2, -1, wait_ap_stopped, (void *)0);
- printk(BIOS_DEBUG, "\n");
-}
-
-static void enable_apic_ext_id(u32 node)
-{
- u32 val;
-
- val = pci_read_config32(NODE_HT(node), 0x68);
- val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
- pci_write_config32(NODE_HT(node), 0x68, val);
-}
-
-static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid)
-{
- msr_t msr;
- uint32_t family;
-
- family = amd_fam1x_cpu_family(); // inline
-
- if (family < 0x6f) {
- /* Family 10h or earlier */
-
- /* Disable L2 IC to L3 connection (Only for CAR) */
- msr = rdmsr(BU_CFG2_MSR);
- msr.lo &= ~(1 << ClLinesToNbDis);
- wrmsr(BU_CFG2_MSR, msr);
- } else {
- /* Family 15h or later
- * DRAM setup is delayed on Fam15 in order to prevent
- * any DRAM access before ECC check bits are initialized.
- * Each core also needs to have its initial DRAM map initialized
- * before it is put to sleep, otherwise it will fail to wake
- * in ramstage. To meet both of these goals, delay DRAM map
- * setup until the last possible moment, where speculative
- * memory access is highly unlikely before core halt...
- */
- if (!skip_sharedc_config) {
- /* Enable memory access for first MBs using top_mem */
- msr.hi = 0;
- msr.lo = (CONFIG_RAMTOP + TOP_MEM_MASK) & (~TOP_MEM_MASK);
- wrmsr(TOP_MEM, msr);
- }
- }
-
- disable_cache_as_ram_real(skip_sharedc_config); // inline
-
- /* Mark the core as sleeping */
- lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_ASLEEP);
-
- /* stop all cores except node0/core0 the bsp .... */
- stop_this_cpu();
-}
-
-u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
-{
- uint32_t bsp_apicid = 0;
- uint32_t apicid;
- uint32_t dword;
- uint8_t set_mtrrs;
- uint8_t node_count;
- uint8_t fam15_bsp_core1_apicid;
- struct node_core_id id;
-
- /* Please refer to the calculations and explaination in cache_as_ram.inc
- * before modifying these values */
- uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE;
- uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_TOP_STACK_SIZE +
- CONFIG_DCACHE_BSP_TOP_STACK_SLUSH;
- uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE +
- CONFIG_DCACHE_RAM_SIZE;
- uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary -
- max_bsp_stack_region_size;
-
- void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary -
- max_ap_stack_region_size);
-
- if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
- printk(BIOS_WARNING,
- "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",
- sysinfo, sysinfo + 1, lower_stack_region_boundary);
-
- /*
- * already set early mtrr in cache_as_ram.inc
- */
-
- /* that is from initial apicid, we need nodeid and coreid
- later */
- id = get_node_core_id_x();
-
- /* NB_CFG MSR is shared between cores, so we need make sure
- core0 is done at first --- use wait_all_core0_started */
- if (id.coreid == 0) {
- /* Set InitApicIdCpuIdLo / EnableCf8ExtCfg on core0 only */
- if (!is_fam15h())
- set_apicid_cpuid_lo();
- set_EnableCf8ExtCfg();
-#if CONFIG(ENABLE_APIC_EXT_ID)
- enable_apic_ext_id(id.nodeid);
-#endif
- }
-
- enable_lapic();
-
-#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
- u32 initial_apicid = get_initial_apicid();
-
-#if !CONFIG(LIFT_BSP_APIC_ID)
- if (initial_apicid != 0) // other than bsp
-#endif
- {
- /* use initial APIC id to lift it */
- u32 dword = lapic_read(LAPIC_ID);
- dword &= ~(0xff << 24);
- dword |=
- (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24);
-
- lapic_write(LAPIC_ID, dword);
- }
-#if CONFIG(LIFT_BSP_APIC_ID)
- bsp_apicid += CONFIG_APIC_ID_OFFSET;
-#endif
-
-#endif
-
- /* get the apicid, it may be lifted already */
- apicid = lapicid();
-
- // show our apicid, nodeid, and coreid
- if (id.coreid == 0) {
- if (id.nodeid != 0) //all core0 except bsp
- print_apicid_nodeid_coreid(apicid, id, " core0: ");
- } else { //all other cores
- print_apicid_nodeid_coreid(apicid, id, " corex: ");
- }
-
- if (cpu_init_detectedx) {
- print_apicid_nodeid_coreid(apicid, id,
- "\n\n\nINIT detected from ");
- printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n");
- soft_reset();
- }
-
- if (id.coreid == 0) {
- if (!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets?
- distinguish_cpu_resets(id.nodeid); // Also indicates we are started
- }
- // Mark the core as started.
- lapic_write(LAPIC_MSG_REG, (apicid << 24) | F10_APSTATE_STARTED);
- printk(BIOS_DEBUG, "CPU APICID %02x start flag set\n", apicid);
-
- if (apicid != bsp_apicid) {
- /* Setup each AP's cores MSRs.
- * This happens after HTinit.
- * The BSP runs this code in it's own path.
- */
- update_microcode(cpuid_eax(1));
-
- cpuSetAMDMSR(id.nodeid);
-
- /* Set up HyperTransport probe filter support */
- if (is_gt_rev_d()) {
- dword = pci_read_config32(NODE_PCI(id.nodeid, 0), 0x60);
- node_count = ((dword >> 4) & 0x7) + 1;
-
- if (node_count > 1) {
- msr_t msr = rdmsr(BU_CFG2_MSR);
- msr.hi |= 1 << (42 - 32);
- wrmsr(BU_CFG2_MSR, msr);
- }
- }
-
-#if CONFIG(SET_FIDVID)
-#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY)
- // Run on all AP for proper FID/VID setup.
- if (id.coreid == 0) // only need set fid for core0
-#endif
- {
- // check warm(bios) reset to call stage2 otherwise do stage1
- if (warm_reset_detect(id.nodeid)) {
- printk(BIOS_DEBUG,
- "init_fidvid_stage2 apicid: %02x\n",
- apicid);
- init_fidvid_stage2(apicid, id.nodeid);
- } else {
- printk(BIOS_DEBUG,
- "init_fidvid_ap(stage1) apicid: %02x\n",
- apicid);
- init_fidvid_ap(apicid, id.nodeid, id.coreid);
- }
- }
-#endif
-
- if (is_fam15h()) {
- /* core 1 on node 0 is special; to avoid corrupting the
- * BSP do not alter MTRRs on that core */
- fam15_bsp_core1_apicid = 1;
- if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
- fam15_bsp_core1_apicid += CONFIG_APIC_ID_OFFSET;
-
- if (apicid == fam15_bsp_core1_apicid)
- set_mtrrs = 0;
- else
- set_mtrrs = !!(apicid & 0x1);
- } else {
- set_mtrrs = 1;
- }
-
- /* AP is ready, configure MTRRs and go to sleep */
- if (set_mtrrs)
- set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
- printk(BIOS_DEBUG, "Disabling CAR on AP %02x\n", apicid);
- if (is_fam15h()) {
- /* Only modify the MSRs on the odd cores (the last cores to finish booting) */
- STOP_CAR_AND_CPU(!set_mtrrs, apicid);
- } else {
- /* Modify MSRs on all cores */
- STOP_CAR_AND_CPU(0, apicid);
- }
-
- printk(BIOS_DEBUG,
- "\nAP %02x should be halted but you are reading this....\n",
- apicid);
- }
-
- return bsp_apicid;
-}
-
-static u32 is_core0_started(u32 nodeid)
-{
- u32 htic;
- pci_devfn_t device;
- device = NODE_PCI(nodeid, 0);
- htic = pci_read_config32(device, HT_INIT_CONTROL);
- htic &= HTIC_ColdR_Detect;
- return htic;
-}
-
-void wait_all_core0_started(void)
-{
- /* When core0 is started, it will distingush_cpu_resets
- * So wait for that to finish */
- u32 i;
- u32 nodes = get_nodes();
-
- printk(BIOS_DEBUG, "core0 started: ");
- for (i = 1; i < nodes; i++) { // skip bsp, because it is running on bsp
- while (!is_core0_started(i)) {
- }
- printk(BIOS_DEBUG, " %02x", i);
- }
- printk(BIOS_DEBUG, "\n");
-}
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
-/**
- * void start_node(u32 node)
- *
- * start the core0 in node, so it can generate HT packet to feature code.
- *
- * This function starts the AP nodes core0s. wait_all_core0_started() in
- * romstage.c waits for all the AP to be finished before continuing
- * system init.
- */
-static void start_node(u8 node)
-{
- u32 val;
-
- /* Enable routing table */
- printk(BIOS_DEBUG, "Start node %02x", node);
-
-#if 0
- /* For FAM10 support, we need to set Dram base/limit for the new node */
- pci_write_config32(NODE_MP(node), 0x44, 0);
- pci_write_config32(NODE_MP(node), 0x40, 3);
-#endif
-
- /* Allow APs to make requests (ROM fetch) */
- val = pci_read_config32(NODE_HT(node), 0x6c);
- val &= ~(1 << 1);
- pci_write_config32(NODE_HT(node), 0x6c, val);
-
- printk(BIOS_DEBUG, " done.\n");
-}
-
-/**
- * static void setup_remote_node(u32 node)
- *
- * Copy the BSP Address Map to each AP.
- */
-static void setup_remote_node(u8 node)
-{
- /* There registers can be used with F1x114_x Address Map at the
- same time, So must set them even 32 node */
- static const u16 pci_reg[] = {
- /* DRAM Base/Limits Registers */
- 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
- 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
- 0x144, 0x14c, 0x154, 0x15c, 0x164, 0x16c, 0x174, 0x17c,
- 0x140, 0x148, 0x150, 0x158, 0x160, 0x168, 0x170, 0x178,
- /* MMIO Base/Limits Registers */
- 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
- 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
- /* IO Base/Limits Registers */
- 0xc4, 0xcc, 0xd4, 0xdc,
- 0xc0, 0xc8, 0xd0, 0xd8,
- /* Configuration Map Registers */
- 0xe0, 0xe4, 0xe8, 0xec,
- };
- u16 i;
-
- printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
-
- /* copy the default resource map from node 0 */
- for (i = 0; i < ARRAY_SIZE(pci_reg); i++) {
- u32 value;
- u16 reg;
- reg = pci_reg[i];
- value = pci_read_config32(NODE_MP(0), reg);
- pci_write_config32(NODE_MP(node), reg, value);
-
- }
- printk(BIOS_DEBUG, " done\n");
-}
-#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
-
-//it is running on core0 of node0
-void start_other_cores(uint32_t bsp_apicid)
-{
- u32 nodes;
- u32 nodeid;
-
- // disable multi_core
- if (read_option(multi_core, 0) != 0) {
- printk(BIOS_DEBUG, "Skip additional core init\n");
- return;
- }
-
- nodes = get_nodes();
-
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- u32 cores = get_core_num_in_bsp(nodeid);
- printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n", nodeid, cores);
- if (cores > 0) {
- real_start_other_core(nodeid, cores);
-#ifdef FAM10_AP_NODE_SEQUENTIAL_START
- printk(BIOS_DEBUG, "waiting for core start on node %d...\n", nodeid);
- for_each_ap(bsp_apicid, 2, nodeid, wait_ap_started, (void *)0);
- printk(BIOS_DEBUG, "...started\n");
-#endif
- }
- }
-}
-
-static void AMD_Errata281(u8 node, uint64_t revision, u32 platform)
-{
- /* Workaround for Transaction Scheduling Conflict in
- * Northbridge Cross Bar. Implement XCS Token adjustment
- * for ganged links. Also, perform fix up for the mixed
- * revision case.
- */
-
- u32 reg, val;
- u8 i;
- u8 mixed = 0;
- u8 nodes = get_nodes();
-
- if (platform & AMD_PTYPE_SVR) {
- /* For each node we need to check for a "broken" node */
- if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) {
- for (i = 0; i < nodes; i++) {
- if (mctGetLogicalCPUID(i) &
- (AMD_DR_B0 | AMD_DR_B1)) {
- mixed = 1;
- break;
- }
- }
- }
-
- if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) {
-
- /* F0X68[22:21] DsNpReqLmt0 = 01b */
- val = pci_read_config32(NODE_PCI(node, 0), 0x68);
- val &= ~0x00600000;
- val |= 0x00200000;
- pci_write_config32(NODE_PCI(node, 0), 0x68, val);
-
- /* F3X6C */
- val = pci_read_config32(NODE_PCI(node, 3), 0x6C);
- val &= ~0x700780F7;
- val |= 0x00010094;
- pci_write_config32(NODE_PCI(node, 3), 0x6C, val);
-
- /* F3X7C */
- val = pci_read_config32(NODE_PCI(node, 3), 0x7C);
- val &= ~0x707FFF1F;
- val |= 0x00144514;
- pci_write_config32(NODE_PCI(node, 3), 0x7C, val);
-
- /* F3X144[3:0] RspTok = 0001b */
- val = pci_read_config32(NODE_PCI(node, 3), 0x144);
- val &= ~0x0000000F;
- val |= 0x00000001;
- pci_write_config32(NODE_PCI(node, 3), 0x144, val);
-
- for (i = 0; i < 3; i++) {
- reg = 0x148 + (i * 4);
- val = pci_read_config32(NODE_PCI(node, 3), reg);
- val &= ~0x000000FF;
- val |= 0x000000DB;
- pci_write_config32(NODE_PCI(node, 3), reg, val);
- }
- }
- }
-}
-
-static void AMD_Errata298(void)
-{
- /* Workaround for L2 Eviction May Occur during operation to
- * set Accessed or dirty bit.
- */
-
- msr_t msr;
- u8 i;
- u8 affectedRev = 0;
- u8 nodes = get_nodes();
-
- /* For each core we need to check for a "broken" node */
- for (i = 0; i < nodes; i++) {
- if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) {
- affectedRev = 1;
- break;
- }
- }
-
- if (affectedRev) {
- msr = rdmsr(HWCR_MSR);
- msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */
- wrmsr(HWCR_MSR, msr);
-
- msr = rdmsr(BU_CFG_MSR);
- msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */
- wrmsr(BU_CFG_MSR, msr);
-
- msr = rdmsr(OSVW_ID_Length);
- msr.lo |= 0x01; /* OS Visible Workaround - MSR */
- wrmsr(OSVW_ID_Length, msr);
-
- msr = rdmsr(OSVW_Status);
- msr.lo |= 0x01; /* OS Visible Workaround - MSR */
- wrmsr(OSVW_Status, msr);
- }
-
- if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) {
- msr = rdmsr(OSVW_ID_Length);
- msr.lo |= 0x01; /* OS Visible Workaround - MSR */
- wrmsr(OSVW_ID_Length, msr);
-
- }
-}
-
-static u32 get_platform_type(void)
-{
- u32 ret = 0;
-
- switch (SYSTEM_TYPE) {
- case 1:
- ret |= AMD_PTYPE_DSK;
- break;
- case 2:
- ret |= AMD_PTYPE_MOB;
- break;
- case 0:
- ret |= AMD_PTYPE_SVR;
- break;
- default:
- break;
- }
-
- /* FIXME: add UMA support. */
-
- /* All Fam10 are multi core */
- ret |= AMD_PTYPE_MC;
-
- return ret;
-}
-
-static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
-{
- u32 dword;
- int i;
- msr_t msr;
-
- if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) {
-
- /* The following code sets the PSIVID to the lowest support P state
- * assuming that the VID for the lowest power state is below
- * the VDD voltage regulator threshold. (This also assumes that there
- * is a Pstate lower than P0)
- */
-
- for (i = 4; i >= 0; i--) {
- msr = rdmsr(PSTATE_0_MSR + i);
- /* Pstate valid? */
- if (msr.hi & PS_EN_MASK) {
- dword = pci_read_config32(NODE_PCI(i, 3), 0xA0);
- dword &= ~0x7F;
- dword |= (msr.lo >> 9) & 0x7F;
- pci_write_config32(NODE_PCI(i, 3), 0xA0, dword);
- break;
- }
- }
- }
-}
-
-/**
- * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links.
- * HT Phy operations are not valid on links that aren't present, so this
- * prevents invalid accesses.
- *
- * Returns the offset of the link register.
- */
-static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset)
-{
- u32 reg;
- u32 val;
-
- /* get start of CPU HT Host Capabilities */
- val = pci_read_config32(NODE_PCI(node, 0), 0x34);
- val &= 0xFF; //reg offset of first link
-
- cap_count++;
-
- /* Traverse through the capabilities. */
- do {
- reg = pci_read_config32(NODE_PCI(node, 0), val);
- /* Is the capability block a HyperTransport capability block? */
- if ((reg & 0xFF) == 0x08) {
- /* Is the HT capability block an HT Host Capability? */
- if ((reg & 0xE0000000) == (1 << 29))
- cap_count--;
- }
-
- if (cap_count)
- val = (reg >> 8) & 0xFF; //update reg offset
- } while (cap_count && val);
-
- *offset = (u8) val;
-
- /* If requested capability found val != 0 */
- if (!cap_count)
- return TRUE;
- else
- return FALSE;
-}
-
-/**
- * AMD_checkLinkType - Compare desired link characteristics using a logical
- * link type mask.
- *
- * Returns the link characteristic mask.
- */
-static u32 AMD_checkLinkType(u8 node, u8 regoff)
-{
- uint32_t val;
- uint32_t val2;
- uint32_t linktype = 0;
-
- /* Check connect, init and coherency */
- val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18);
- val &= 0x1F;
-
- if (val == 3)
- linktype |= HTPHY_LINKTYPE_COHERENT;
-
- if (val == 7)
- linktype |= HTPHY_LINKTYPE_NONCOHERENT;
-
- if (linktype) {
- /* Check gen3 */
- val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08);
- val = (val >> 8) & 0xf;
- if (is_gt_rev_d()) {
- val2 = pci_read_config32(NODE_PCI(node, 0), regoff + 0x1c);
- val |= (val2 & 0x1) << 4;
- }
-
- if (val > 6)
- linktype |= HTPHY_LINKTYPE_HT3;
- else
- linktype |= HTPHY_LINKTYPE_HT1;
-
- /* Check ganged */
- val = pci_read_config32(NODE_PCI(node, 0), (((regoff - 0x80) / 0x20) << 2) + 0x170);
-
- if (val & 1)
- linktype |= HTPHY_LINKTYPE_GANGED;
- else
- linktype |= HTPHY_LINKTYPE_UNGANGED;
- }
-
- return linktype;
-}
-
-/**
- * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update
- * a phy setting for that link.
- */
-static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry)
-{
- u32 phyReg;
- u32 phyBase;
- u32 val;
-
- /* Determine this link's portal */
- if (link > 3)
- link -= 4;
-
- phyBase = ((u32) link << 3) | 0x180;
-
- /* Determine if link is connected and abort if not */
- if (!(pci_read_config32(NODE_PCI(node, 0), 0x98 + (link * 0x20)) & 0x1))
- return;
-
- /* Get the portal control register's initial value
- * and update it to access the desired phy register
- */
- phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase);
-
- if (fam10_htphy_default[entry].htreg > 0x1FF) {
- phyReg &= ~HTPHY_DIRECT_OFFSET_MASK;
- phyReg |= HTPHY_DIRECT_MAP;
- } else {
- phyReg &= ~HTPHY_OFFSET_MASK;
- }
-
- /* Now get the current phy register data
- * LinkPhyDone = 0, LinkPhyWrite = 0 is a read
- */
- phyReg |= fam10_htphy_default[entry].htreg;
- pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
-
- do {
- val = pci_read_config32(NODE_PCI(node, 4), phyBase);
- } while (!(val & HTPHY_IS_COMPLETE_MASK));
-
- /* Now we have the phy register data, apply the change */
- val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4);
- val &= ~fam10_htphy_default[entry].mask;
- val |= fam10_htphy_default[entry].data;
- pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val);
-
- /* write it through the portal to the phy
- * LinkPhyDone = 0, LinkPhyWrite = 1 is a write
- */
- phyReg |= HTPHY_WRITE_CMD;
- pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
-
- do {
- val = pci_read_config32(NODE_PCI(node, 4), phyBase);
- } while (!(val & HTPHY_IS_COMPLETE_MASK));
-}
-
-void cpuSetAMDMSR(uint8_t node_id)
-{
- /* This routine loads the CPU with default settings in fam10_msr_default
- * table . It must be run after Cache-As-RAM has been enabled, and
- * Hypertransport initialization has taken place. Also note
- * that it is run on the current processor only, and only for the current
- * processor core.
- */
- msr_t msr;
- u8 i;
- uint8_t nvram;
- u32 platform;
- uint64_t revision;
- uint8_t enable_cpb;
-
- printk(BIOS_DEBUG, "cpuSetAMDMSR ");
-
- revision = mctGetLogicalCPUID(0xFF);
- platform = get_platform_type();
-
- for (i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) {
- if ((fam10_msr_default[i].revision & revision) &&
- (fam10_msr_default[i].platform & platform)) {
- msr = rdmsr(fam10_msr_default[i].msr);
- msr.hi &= ~fam10_msr_default[i].mask_hi;
- msr.hi |= fam10_msr_default[i].data_hi;
- msr.lo &= ~fam10_msr_default[i].mask_lo;
- msr.lo |= fam10_msr_default[i].data_lo;
- wrmsr(fam10_msr_default[i].msr, msr);
- }
- }
- AMD_Errata298();
-
- /* Revision C0 and above */
- if (revision & AMD_OR_C0) {
- uint8_t enable_experimental_memory_speed_boost;
-
- /* Check to see if cache partitioning is allowed */
- enable_experimental_memory_speed_boost = 0;
- if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS)
- enable_experimental_memory_speed_boost = !!nvram;
-
- uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc);
- msr = rdmsr(FP_CFG_MSR);
- msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */
- msr.hi |= (((f3x1fc >> 17) & 0x7) << (42-32));
- msr.hi &= ~(0x1 << (41-32)); /* DiDtCfg5 */
- msr.hi |= (((f3x1fc >> 22) & 0x1) << (41-32));
- msr.hi &= ~(0x1 << (40-32)); /* DiDtCfg3 */
- msr.hi |= (((f3x1fc >> 16) & 0x1) << (40-32));
- msr.hi &= ~(0x7 << (32-32)); /* DiDtCfg1 (1) */
- msr.hi |= (((f3x1fc >> 11) & 0x7) << (32-32));
- msr.lo &= ~(0x1f << 27); /* DiDtCfg1 (2) */
- msr.lo |= (((f3x1fc >> 6) & 0x1f) << 27);
- msr.lo &= ~(0x3 << 25); /* DiDtCfg2 */
- msr.lo |= (((f3x1fc >> 14) & 0x3) << 25);
- msr.lo &= ~(0x1f << 18); /* DiDtCfg0 */
- msr.lo |= (((f3x1fc >> 1) & 0x1f) << 18);
- msr.lo &= ~(0x1 << 16); /* DiDtMode */
- msr.lo |= ((f3x1fc & 0x1) << 16);
- wrmsr(FP_CFG_MSR, msr);
-
- if (enable_experimental_memory_speed_boost) {
- msr = rdmsr(BU_CFG3_MSR);
- msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */
- wrmsr(BU_CFG3_MSR, msr);
- }
- }
-
- if (revision & AMD_FAM15_ALL) {
- enable_cpb = 1;
- if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS)
- enable_cpb = !!nvram;
-
- if (!enable_cpb) {
- /* Disable Core Performance Boost */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (0x1 << 25); /* CpbDis = 1 */
- wrmsr(HWCR_MSR, msr);
- }
- }
-
- printk(BIOS_DEBUG, " done\n");
-}
-
-static void cpuSetAMDPCI(u8 node)
-{
- /* This routine loads the CPU with default settings in fam10_pci_default
- * table . It must be run after Cache-As-RAM has been enabled, and
- * Hypertransport initialization has taken place. Also note
- * that it is run for the first core on each node
- */
- uint8_t i;
- uint8_t j;
- u32 platform;
- u32 val;
- uint8_t offset;
- uint32_t dword;
- uint64_t revision;
-
- /* FIXME
- * This should be configurable
- */
- uint8_t sockets = 2;
- uint8_t sockets_populated = 2;
-
- printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
-
- revision = mctGetLogicalCPUID(node);
- platform = get_platform_type();
-
- AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */
-
- for (i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) {
- if ((fam10_pci_default[i].revision & revision) &&
- (fam10_pci_default[i].platform & platform)) {
- val = pci_read_config32(NODE_PCI(node,
- fam10_pci_default[i].
- function),
- fam10_pci_default[i].offset);
- val &= ~fam10_pci_default[i].mask;
- val |= fam10_pci_default[i].data;
- pci_write_config32(NODE_PCI(node,
- fam10_pci_default[i].
- function),
- fam10_pci_default[i].offset, val);
- }
- }
-
- if (is_fam15h()) {
- if (CONFIG_CPU_SOCKET_TYPE == 0x14) {
- /* Socket C32 */
- dword = pci_read_config32(NODE_PCI(node, 0), 0x84);
- dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
- pci_write_config32(NODE_PCI(node, 0), 0x84, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), 0xa4);
- dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
- pci_write_config32(NODE_PCI(node, 0), 0xa4, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), 0xc4);
- dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
- pci_write_config32(NODE_PCI(node, 0), 0xc4, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), 0xe4);
- dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
- pci_write_config32(NODE_PCI(node, 0), 0xe4, dword);
- }
- else {
- /* Other socket (G34, etc.) */
- dword = pci_read_config32(NODE_PCI(node, 0), 0x84);
- dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
- pci_write_config32(NODE_PCI(node, 0), 0x84, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), 0xa4);
- dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
- pci_write_config32(NODE_PCI(node, 0), 0xa4, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), 0xc4);
- dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
- pci_write_config32(NODE_PCI(node, 0), 0xc4, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), 0xe4);
- dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
- pci_write_config32(NODE_PCI(node, 0), 0xe4, dword);
- }
- }
-
-#ifdef DEBUG_HT_SETUP
- /* Dump link settings */
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 4; j++) {
- printk(BIOS_DEBUG, "Node %d link %d: type register: %08x control register: %08x extended control sublink 0: %08x 1: %08x\n", i, j,
- pci_read_config32(NODE_PCI(i, 0), 0x98 + (j * 0x20)), pci_read_config32(NODE_PCI(i, 0), 0x84 + (j * 0x20)),
- pci_read_config32(NODE_PCI(i, 0), 0x170 + (j * 0x4)), pci_read_config32(NODE_PCI(i, 0), 0x180 + (j * 0x4)));
- }
- }
-#endif
-
- for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) {
- if ((fam10_htphy_default[i].revision & revision) &&
- (fam10_htphy_default[i].platform & platform)) {
- /* HT Phy settings either apply to both sublinks or have
- * separate registers for sublink zero and one, so there
- * will be two table entries. So, here we only loop
- * through the sublink zeros in function zero.
- */
- for (j = 0; j < 4; j++) {
- if (AMD_CpuFindCapability(node, j, &offset)) {
- if (AMD_checkLinkType(node, offset)
- & fam10_htphy_default[i].linktype) {
- AMD_SetHtPhyRegister(node, j,
- i);
- }
- } else {
- /* No more capabilities,
- * link not present
- */
- break;
- }
- }
- }
- }
-
- /* FIXME: add UMA support and programXbarToSriReg(); */
-
- AMD_Errata281(node, revision, platform);
-
- /* FIXME: if the dct phy doesn't init correct it needs to reset.
- if (revision & (AMD_DR_B2 | AMD_DR_B3))
- dctPhyDiag(); */
-
- if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
- /* Set up message triggered C1E */
- dword = pci_read_config32(NODE_PCI(node, 3), 0xd4);
- dword &= ~(0x1 << 14); /* CacheFlushImmOnAllHalt = !is_fam15h() */
- dword |= (is_fam15h()?0:1) << 14;
- pci_write_config32(NODE_PCI(node, 3), 0xd4, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0xdc);
- dword |= 0x1 << 26; /* IgnCpuPrbEn = 1 */
- dword &= ~(0x7f << 19); /* CacheFlushOnHaltTmr = 0x28 */
- dword |= 0x28 << 19;
- dword |= 0x7 << 16; /* CacheFlushOnHaltCtl = 0x7 */
- pci_write_config32(NODE_PCI(node, 3), 0xdc, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0xa0);
- dword |= 0x1 << 10; /* IdleExitEn = 1 */
- pci_write_config32(NODE_PCI(node, 3), 0xa0, dword);
-
- if (revision & AMD_DR_GT_D0) {
- dword = pci_read_config32(NODE_PCI(node, 3), 0x188);
- dword |= 0x1 << 4; /* EnStpGntOnFlushMaskWakeup = 1 */
- pci_write_config32(NODE_PCI(node, 3), 0x188, dword);
- } else {
- dword = pci_read_config32(NODE_PCI(node, 4), 0x128);
- dword &= ~(0x1 << 31); /* CstateMsgDis = 0 */
- pci_write_config32(NODE_PCI(node, 4), 0x128, dword);
- }
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0xd4);
- dword |= 0x1 << 13; /* MTC1eEn = 1 */
- pci_write_config32(NODE_PCI(node, 3), 0xd4, dword);
- }
-
- if (revision & AMD_FAM15_ALL) {
- uint32_t f5x80;
- uint8_t cu_enabled;
- uint8_t compute_unit_count = 0;
- uint8_t compute_unit_buffer_count;
-
- uint32_t f3xe8;
- uint8_t dual_node = 0;
-
- f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
-
- /* Check for dual node capability */
- if (f3xe8 & 0x20000000)
- dual_node = 1;
-
- /* Determine the number of active compute units on this node */
- f5x80 = pci_read_config32(NODE_PCI(node, 5), 0x80);
- cu_enabled = f5x80 & 0xf;
- if (cu_enabled == 0x1)
- compute_unit_count = 1;
- if (cu_enabled == 0x3)
- compute_unit_count = 2;
- if (cu_enabled == 0x7)
- compute_unit_count = 3;
- if (cu_enabled == 0xf)
- compute_unit_count = 4;
-
- if (compute_unit_count == 1)
- compute_unit_buffer_count = 0x1c;
- else if (compute_unit_count == 2)
- compute_unit_buffer_count = 0x18;
- else if (compute_unit_count == 3)
- compute_unit_buffer_count = 0x14;
- else
- compute_unit_buffer_count = 0x10;
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0x1a0);
- dword &= ~(0x1f << 4); /* L3FreeListCBC = compute_unit_buffer_count */
- dword |= (compute_unit_buffer_count << 4);
- pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword);
-
- uint8_t link;
- uint8_t link_real;
- uint8_t ganged;
- uint8_t iolink;
- uint8_t probe_filter_enabled = !!dual_node;
-
- /* Set up the Link Base Channel Buffer Count */
- uint8_t isoc_rsp_data;
- uint8_t isoc_np_req_data;
- uint8_t isoc_rsp_cmd;
- uint8_t isoc_preq;
- uint8_t isoc_np_req_cmd;
- uint8_t free_data;
- uint8_t free_cmd;
- uint8_t rsp_data;
- uint8_t np_req_data;
- uint8_t probe_cmd;
- uint8_t rsp_cmd;
- uint8_t preq;
- uint8_t np_req_cmd;
-
- /* Common settings for all links and system configurations */
- isoc_rsp_data = 0;
- isoc_np_req_data = 0;
- isoc_rsp_cmd = 0;
- isoc_preq = 0;
- isoc_np_req_cmd = 1;
- free_cmd = 8;
-
- for (link = 0; link < 4; link++) {
- if (AMD_CpuFindCapability(node, link, &offset)) {
- link_real = (offset - 0x80) / 0x20;
- ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link_real << 2) + 0x170) & 0x1);
- iolink = !!(AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_NONCOHERENT);
-
- if (!iolink && ganged) {
- if (probe_filter_enabled) {
- free_data = 0;
- rsp_data = 3;
- np_req_data = 3;
- probe_cmd = 4;
- rsp_cmd = 9;
- preq = 2;
- np_req_cmd = 8;
- } else {
- free_data = 0;
- rsp_data = 3;
- np_req_data = 3;
- probe_cmd = 8;
- rsp_cmd = 9;
- preq = 2;
- np_req_cmd = 4;
- }
- } else if (!iolink && !ganged) {
- if (probe_filter_enabled) {
- free_data = 0;
- rsp_data = 3;
- np_req_data = 3;
- probe_cmd = 4;
- rsp_cmd = 9;
- preq = 2;
- np_req_cmd = 8;
- } else {
- free_data = 0;
- rsp_data = 3;
- np_req_data = 3;
- probe_cmd = 8;
- rsp_cmd = 9;
- preq = 2;
- np_req_cmd = 4;
- }
- } else if (iolink && ganged) {
- free_data = 0;
- rsp_data = 1;
- np_req_data = 0;
- probe_cmd = 0;
- rsp_cmd = 2;
- preq = 7;
- np_req_cmd = 14;
- } else {
- /* FIXME
- * This is an educated guess as the BKDG does not specify
- * the appropriate buffer counts for this case!
- */
- free_data = 1;
- rsp_data = 1;
- np_req_data = 1;
- probe_cmd = 0;
- rsp_cmd = 2;
- preq = 4;
- np_req_cmd = 12;
- }
-
- dword = pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x94);
- dword &= ~(0x3 << 27); /* IsocRspData = isoc_rsp_data */
- dword |= ((isoc_rsp_data & 0x3) << 27);
- dword &= ~(0x3 << 25); /* IsocNpReqData = isoc_np_req_data */
- dword |= ((isoc_np_req_data & 0x3) << 25);
- dword &= ~(0x7 << 22); /* IsocRspCmd = isoc_rsp_cmd */
- dword |= ((isoc_rsp_cmd & 0x7) << 22);
- dword &= ~(0x7 << 19); /* IsocPReq = isoc_preq */
- dword |= ((isoc_preq & 0x7) << 19);
- dword &= ~(0x7 << 16); /* IsocNpReqCmd = isoc_np_req_cmd */
- dword |= ((isoc_np_req_cmd & 0x7) << 16);
- pci_write_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x94, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x90);
- dword &= ~(0x1 << 31); /* LockBc = 0x1 */
- dword |= ((0x1 & 0x1) << 31);
- dword &= ~(0x7 << 25); /* FreeData = free_data */
- dword |= ((free_data & 0x7) << 25);
- dword &= ~(0x1f << 20); /* FreeCmd = free_cmd */
- dword |= ((free_cmd & 0x1f) << 20);
- dword &= ~(0x3 << 18); /* RspData = rsp_data */
- dword |= ((rsp_data & 0x3) << 18);
- dword &= ~(0x3 << 16); /* NpReqData = np_req_data */
- dword |= ((np_req_data & 0x3) << 16);
- dword &= ~(0xf << 12); /* ProbeCmd = probe_cmd */
- dword |= ((probe_cmd & 0xf) << 12);
- dword &= ~(0xf << 8); /* RspCmd = rsp_cmd */
- dword |= ((rsp_cmd & 0xf) << 8);
- dword &= ~(0x7 << 5); /* PReq = preq */
- dword |= ((preq & 0x7) << 5);
- dword &= ~(0x1f << 0); /* NpReqCmd = np_req_cmd */
- dword |= ((np_req_cmd & 0x1f) << 0);
- pci_write_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x90, dword);
- }
- }
-
- /* Set up the Link to XCS Token Counts */
- uint8_t isoc_rsp_tok_1;
- uint8_t isoc_preq_tok_1;
- uint8_t isoc_req_tok_1;
- uint8_t probe_tok_1;
- uint8_t rsp_tok_1;
- uint8_t preq_tok_1;
- uint8_t req_tok_1;
- uint8_t isoc_rsp_tok_0;
- uint8_t isoc_preq_tok_0;
- uint8_t isoc_req_tok_0;
- uint8_t free_tokens;
- uint8_t probe_tok_0;
- uint8_t rsp_tok_0;
- uint8_t preq_tok_0;
- uint8_t req_tok_0;
-
- for (link = 0; link < 4; link++) {
- if (AMD_CpuFindCapability(node, link, &offset)) {
- link_real = (offset - 0x80) / 0x20;
- ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link_real << 2) + 0x170) & 0x1);
- iolink = !!(AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_NONCOHERENT);
-
- /* Set defaults */
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = !ganged;
- rsp_tok_1 = !ganged;
- preq_tok_1 = !ganged;
- req_tok_1 = !ganged;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 0;
- free_tokens = 0;
- probe_tok_0 = ((ganged)?2:1);
- rsp_tok_0 = ((ganged)?2:1);
- preq_tok_0 = ((ganged)?2:1);
- req_tok_0 = ((ganged)?2:1);
-
- if (!iolink && ganged) {
- if (!dual_node) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 3;
- probe_tok_0 = 2;
- rsp_tok_0 = 2;
- preq_tok_0 = 2;
- req_tok_0 = 2;
- } else {
- if ((sockets == 1)
- || ((sockets == 2) && (sockets_populated == 1))) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 2;
- rsp_tok_0 = 2;
- preq_tok_0 = 2;
- req_tok_0 = 2;
- } else if (((sockets == 2) && (sockets_populated == 2))
- || ((sockets == 4) && (sockets_populated == 2))) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 1;
- rsp_tok_0 = 2;
- preq_tok_0 = 2;
- req_tok_0 = 2;
- } else if ((sockets == 4) && (sockets_populated == 4)) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 2;
- rsp_tok_0 = 1;
- preq_tok_0 = 1;
- req_tok_0 = 2;
- }
- }
- } else if (!iolink && !ganged) {
- if ((sockets == 1)
- || ((sockets == 2) && (sockets_populated == 1))) {
- if (probe_filter_enabled) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 1;
- rsp_tok_1 = 1;
- preq_tok_1 = 1;
- req_tok_1 = 1;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 1;
- rsp_tok_0 = 2;
- preq_tok_0 = 1;
- req_tok_0 = 1;
- } else {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 1;
- rsp_tok_1 = 1;
- preq_tok_1 = 1;
- req_tok_1 = 1;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 1;
- rsp_tok_0 = 1;
- preq_tok_0 = 1;
- req_tok_0 = 1;
- }
- } else if ((sockets == 2) && (sockets_populated == 2)) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 1;
- probe_tok_1 = 1;
- rsp_tok_1 = 1;
- preq_tok_1 = 1;
- req_tok_1 = 1;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 2;
- probe_tok_0 = 1;
- rsp_tok_0 = 1;
- preq_tok_0 = 1;
- req_tok_0 = 1;
- } else if ((sockets == 4) && (sockets_populated == 2)) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 1;
- probe_tok_1 = 1;
- rsp_tok_1 = 1;
- preq_tok_1 = 1;
- req_tok_1 = 1;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 4;
- probe_tok_0 = 1;
- rsp_tok_0 = 1;
- preq_tok_0 = 1;
- req_tok_0 = 1;
- } else if ((sockets == 4) && (sockets_populated == 4)) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 1;
- probe_tok_1 = 1;
- rsp_tok_1 = 1;
- preq_tok_1 = 1;
- req_tok_1 = 1;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 1;
- rsp_tok_0 = 1;
- preq_tok_0 = 1;
- req_tok_0 = 1;
- }
- } else if (iolink && ganged) {
- if (!dual_node) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 3;
- probe_tok_0 = 0;
- rsp_tok_0 = 2;
- preq_tok_0 = 2;
- req_tok_0 = 2;
- } else if ((sockets == 1)
- || (sockets == 2)
- || ((sockets == 4) && (sockets_populated == 2))) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 1;
- free_tokens = 0;
- probe_tok_0 = 0;
- rsp_tok_0 = 2;
- preq_tok_0 = 2;
- req_tok_0 = 2;
- } else if ((sockets == 4) && (sockets_populated == 4)) {
- isoc_rsp_tok_1 = 0;
- isoc_preq_tok_1 = 0;
- isoc_req_tok_1 = 0;
- probe_tok_1 = 0;
- rsp_tok_1 = 0;
- preq_tok_1 = 0;
- req_tok_1 = 0;
- isoc_rsp_tok_0 = 0;
- isoc_preq_tok_0 = 0;
- isoc_req_tok_0 = 2;
- free_tokens = 0;
- probe_tok_0 = 2;
- rsp_tok_0 = 2;
- preq_tok_0 = 2;
- req_tok_0 = 2;
- }
- }
-
- dword = pci_read_config32(NODE_PCI(node, 3), (link_real << 2) + 0x148);
- dword &= ~(0x3 << 30); /* FreeTok[3:2] = free_tokens[3:2] */
- dword |= (((free_tokens >> 2) & 0x3) << 30);
- dword &= ~(0x1 << 28); /* IsocRspTok1 = isoc_rsp_tok_1 */
- dword |= (((isoc_rsp_tok_1) & 0x1) << 28);
- dword &= ~(0x1 << 26); /* IsocPreqTok1 = isoc_preq_tok_1 */
- dword |= (((isoc_preq_tok_1) & 0x1) << 26);
- dword &= ~(0x1 << 24); /* IsocReqTok1 = isoc_req_tok_1 */
- dword |= (((isoc_req_tok_1) & 0x1) << 24);
- dword &= ~(0x3 << 22); /* ProbeTok1 = probe_tok_1 */
- dword |= (((probe_tok_1) & 0x3) << 22);
- dword &= ~(0x3 << 20); /* RspTok1 = rsp_tok_1 */
- dword |= (((rsp_tok_1) & 0x3) << 20);
- dword &= ~(0x3 << 18); /* PReqTok1 = preq_tok_1 */
- dword |= (((preq_tok_1) & 0x3) << 18);
- dword &= ~(0x3 << 16); /* ReqTok1 = req_tok_1 */
- dword |= (((req_tok_1) & 0x3) << 16);
- dword &= ~(0x3 << 14); /* FreeTok[1:0] = free_tokens[1:0] */
- dword |= (((free_tokens) & 0x3) << 14);
- dword &= ~(0x3 << 12); /* IsocRspTok0 = isoc_rsp_tok_0 */
- dword |= (((isoc_rsp_tok_0) & 0x3) << 12);
- dword &= ~(0x3 << 10); /* IsocPreqTok0 = isoc_preq_tok_0 */
- dword |= (((isoc_preq_tok_0) & 0x3) << 10);
- dword &= ~(0x3 << 8); /* IsocReqTok0 = isoc_req_tok_0 */
- dword |= (((isoc_req_tok_0) & 0x3) << 8);
- dword &= ~(0x3 << 6); /* ProbeTok0 = probe_tok_0 */
- dword |= (((probe_tok_0) & 0x3) << 6);
- dword &= ~(0x3 << 4); /* RspTok0 = rsp_tok_0 */
- dword |= (((rsp_tok_0) & 0x3) << 4);
- dword &= ~(0x3 << 2); /* PReqTok0 = preq_tok_0 */
- dword |= (((preq_tok_0) & 0x3) << 2);
- dword &= ~(0x3 << 0); /* ReqTok0 = req_tok_0 */
- dword |= (((req_tok_0) & 0x3) << 0);
- pci_write_config32(NODE_PCI(node, 3), (link_real << 2) + 0x148, dword);
- }
- }
-
- /* Set up the SRI to XCS Token Count */
- uint8_t free_tok;
- uint8_t up_rsp_tok;
-
- /* Set defaults */
- free_tok = 0xa;
- up_rsp_tok = 0x3;
-
- if (!dual_node) {
- free_tok = 0xa;
- up_rsp_tok = 0x3;
- } else {
- if ((sockets == 1)
- || ((sockets == 2) && (sockets_populated == 1))) {
- if (probe_filter_enabled) {
- free_tok = 0x9;
- up_rsp_tok = 0x3;
- } else {
- free_tok = 0xa;
- up_rsp_tok = 0x3;
- }
- } else if ((sockets == 2) && (sockets_populated == 2)) {
- free_tok = 0xb;
- up_rsp_tok = 0x1;
- } else if ((sockets == 4) && (sockets_populated == 2)) {
- free_tok = 0xa;
- up_rsp_tok = 0x3;
- } else if ((sockets == 4) && (sockets_populated == 4)) {
- free_tok = 0x9;
- up_rsp_tok = 0x1;
- }
- }
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0x140);
- dword &= ~(0xf << 20); /* FreeTok = free_tok */
- dword |= ((free_tok & 0xf) << 20);
- dword &= ~(0x3 << 8); /* UpRspTok = up_rsp_tok */
- dword |= ((up_rsp_tok & 0x3) << 8);
- pci_write_config32(NODE_PCI(node, 3), 0x140, dword);
- }
-
- uint8_t link;
- uint8_t link_real;
- uint8_t isochronous;
- uint8_t isochronous_link_present;
-
- /* Set up isochronous buffers if needed */
- isochronous_link_present = 0;
- if (revision & AMD_FAM15_ALL) {
- for (link = 0; link < 4; link++) {
- if (AMD_CpuFindCapability(node, link, &offset)) {
- link_real = (offset - 0x80) / 0x20;
- isochronous = (pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x84) >> 12) & 0x1;
-
- if (isochronous)
- isochronous_link_present = 1;
- }
- }
- }
-
- uint8_t free_tok;
- uint8_t up_rsp_cbc;
- uint8_t isoc_preq_cbc;
- uint8_t isoc_preq_tok;
- uint8_t xbar_to_sri_free_list_cbc;
- if (isochronous_link_present) {
- /* Adjust buffer counts */
- dword = pci_read_config32(NODE_PCI(node, 3), 0x70);
- isoc_preq_cbc = (dword >> 24) & 0x7;
- up_rsp_cbc = (dword >> 16) & 0x7;
- up_rsp_cbc--;
- isoc_preq_cbc++;
- dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */
- dword |= ((isoc_preq_cbc & 0x7) << 24);
- dword &= ~(0x7 << 16); /* UpRspCBC = up_rsp_cbc */
- dword |= ((up_rsp_cbc & 0x7) << 16);
- pci_write_config32(NODE_PCI(node, 3), 0x70, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0x74);
- isoc_preq_cbc = (dword >> 24) & 0x7;
- isoc_preq_cbc++;
- dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */
- dword |= (isoc_preq_cbc & 0x7) << 24;
- pci_write_config32(NODE_PCI(node, 3), 0x74, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0x7c);
- xbar_to_sri_free_list_cbc = dword & 0x1f;
- xbar_to_sri_free_list_cbc--;
- dword &= ~0x1f; /* Xbar2SriFreeListCBC = xbar_to_sri_free_list_cbc */
- dword |= xbar_to_sri_free_list_cbc & 0x1f;
- pci_write_config32(NODE_PCI(node, 3), 0x7c, dword);
-
- dword = pci_read_config32(NODE_PCI(node, 3), 0x140);
- free_tok = (dword >> 20) & 0xf;
- isoc_preq_tok = (dword >> 14) & 0x3;
- free_tok--;
- isoc_preq_tok++;
- dword &= ~(0xf << 20); /* FreeTok = free_tok */
- dword |= ((free_tok & 0xf) << 20);
- dword &= ~(0x3 << 14); /* IsocPreqTok = isoc_preq_tok */
- dword |= ((isoc_preq_tok & 0x3) << 14);
- pci_write_config32(NODE_PCI(node, 3), 0x140, dword);
- }
-
- printk(BIOS_DEBUG, " done\n");
-}
-
-#ifdef UNUSED_CODE
-/* Clearing the MCA registers is apparently handled in the ramstage CPU Function 3 driver */
-static void cpuInitializeMCA(void)
-{
- /* Clears Machine Check Architecture (MCA) registers, which power on
- * containing unknown data, on currently running processor.
- * This routine should only be executed on initial power on (cold boot),
- * not across a warm reset because valid data is present at that time.
- */
-
- msr_t msr;
- u32 reg;
- u8 i;
-
- if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */
- msr = rdmsr(IA32_MCG_CAP);
- if (msr.lo & MCG_CTL_P) { /* MCG_CTL_P bit is set? */
- msr.lo &= 0xFF;
- msr.lo--;
- msr.lo <<= 2; /* multiply the count by 4 */
- reg = IA32_MC0_STATUS + msr.lo;
- msr.lo = msr.hi = 0;
- for (i = 0; i < 4; i++) {
- wrmsr(reg, msr);
- reg -= 4; /* Touch status regs for each bank */
- }
- }
- }
-}
-#endif
-
-/**
- * finalize_node_setup()
- *
- * Do any additional post HT init
- *
- */
-void finalize_node_setup(struct sys_info *sysinfo)
-{
- u8 i;
- u8 nodes = get_nodes();
- u32 reg;
-
- /* read Node0 F0_0x64 bit [8:10] to find out SbLink # */
- reg = pci_read_config32(NODE_HT(0), 0x64);
- sysinfo->sblk = (reg >> 8) & 7;
- sysinfo->sbbusn = 0;
- sysinfo->nodes = nodes;
- sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
-
- for (i = 0; i < nodes; i++) {
- cpuSetAMDPCI(i);
- }
-
-#if CONFIG(SET_FIDVID)
- // Prep each node for FID/VID setup.
- prep_fid_change();
-#endif
-
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- /* Skip the BSP, start at node 1 */
- for (i = 1; i < nodes; i++) {
- setup_remote_node(i);
- start_node(i);
- }
-#endif
-}
-
-#if CONFIG(SET_FIDVID)
-# include "fidvid.c"
-#endif
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.h b/src/cpu/amd/family_10h-family_15h/init_cpus.h
deleted file mode 100644
index 4be6ee8..0000000
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef INIT_CPUS_H
-#define INIT_CPUS_H
-
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/multicore.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include "defaults.h"
-
-#define NODE_HT(x) NODE_PCI(x,0)
-#define NODE_MP(x) NODE_PCI(x,1)
-#define NODE_MC(x) NODE_PCI(x,3)
-#define NODE_LC(x) NODE_PCI(x,4)
-
-unsigned int get_sbdn(unsigned int bus);
-void cpuSetAMDMSR(uint8_t node_id);
-
-typedef void (*process_ap_t) (u32 apicid, void *gp);
-
-uint32_t get_boot_apic_id(uint8_t node, uint32_t core);
-u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo);
-uint8_t set_apicid_cpuid_lo(void);
-void real_start_other_core(uint32_t nodeid, uint32_t cores);
-void finalize_node_setup(struct sys_info *sysinfo);
-uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2);
-void start_other_cores(uint32_t bsp_apicid);
-u32 get_core_num_in_bsp(u32 nodeid);
-
-void update_microcode(u32 cpu_deviceid);
-
-/* fidvid.c */
-void init_fidvid_stage2(u32 apicid, u32 nodeid);
-void prep_fid_change(void);
-int init_fidvid_bsp(u32 bsp_apicid, u32 nodes);
-
-#endif
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
deleted file mode 100644
index 9c040eb9..0000000
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <cpu/x86/smm.h>
-#include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/multicore.h>
-
-static inline uint8_t is_gt_rev_d(void)
-{
- uint8_t fam15h = 0;
- uint8_t rev_gte_d = 0;
- uint32_t family;
- uint32_t model;
-
- family = model = cpuid_eax(0x80000001);
- model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f)
- /* Family 15h or later */
- fam15h = 1;
-
- if ((model >= 0x8) || fam15h)
- /* Revision D or later */
- rev_gte_d = 1;
-
- return rev_gte_d;
-}
-
-static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }};
-
-static void model_10xxx_init(struct device *dev)
-{
- u8 i;
- msr_t msr;
- int num_banks;
- struct node_core_id id;
-#if CONFIG(LOGICAL_CPUS)
- u32 siblings;
-#endif
- uint8_t delay_start;
-
- id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
- printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
-
- if (is_fam15h())
- delay_start = !!(id.coreid & 0x1);
- else
- delay_start = 0;
-
- /* Turn on caching if we haven't already */
- x86_enable_cache();
-
- if (!delay_start) {
- /* Initialize all variable MTRRs except the first pair.
- * This prevents Linux from having to correct an inconsistent
- * MTRR setup, which would crash Family 15h CPUs due to the
- * compute unit structure sharing MTRR MSRs between AP cores.
- */
- msr.hi = 0x00000000;
- msr.lo = 0x00000000;
-
- disable_cache();
-
- for (i = 0x2; i < 0x10; i++) {
- wrmsr(MTRR_PHYS_BASE(0) | i, msr);
- }
-
- enable_cache();
-
- /* Set up other MTRRs */
- amd_setup_mtrrs();
- } else {
- while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) {
- /* Wait for CU first core startup */
- }
- }
-
- x86_mtrr_check();
-
- disable_cache();
-
- /* zero the machine check error status registers */
- msr = rdmsr(IA32_MCG_CAP);
- num_banks = msr.lo & MCA_BANKS_MASK;
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-
- enable_cache();
-
- /* Enable the local CPU APICs */
- setup_lapic();
-
- /* Set the processor name string */
- init_processor_name();
-
-#if CONFIG(LOGICAL_CPUS)
- siblings = cpuid_ecx(0x80000008) & 0xff;
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
- /* Set bus unit configuration */
- if (is_fam15h()) {
- uint32_t f5x80;
- uint8_t enabled;
- uint8_t compute_unit_count = 0;
- f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5),
- 0x80);
- enabled = f5x80 & 0xf;
- if (enabled == 0x1)
- compute_unit_count = 1;
- if (enabled == 0x3)
- compute_unit_count = 2;
- if (enabled == 0x7)
- compute_unit_count = 3;
- if (enabled == 0xf)
- compute_unit_count = 4;
- msr = rdmsr(BU_CFG2_MSR);
- msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */
- msr.lo |= (((compute_unit_count - 1) & 0x3) << 6);
- wrmsr(BU_CFG2_MSR, msr);
- } else {
- uint32_t f0x60;
- uint32_t f0x160;
- uint8_t core_count = 0;
- uint8_t node_count = 0;
- f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0),
- 0x60);
- core_count = (f0x60 >> 16) & 0x1f;
- node_count = ((f0x60 >> 4) & 0x7) + 1;
- if (is_gt_rev_d()) {
- f0x160 = pci_read_config32(
- pcidev_on_root(0x18 + id.nodeid, 0), 0x160);
- core_count |= ((f0x160 >> 16) & 0x7) << 5;
- }
- core_count++;
- core_count /= node_count;
- msr = rdmsr(BU_CFG2_MSR);
- if (is_gt_rev_d()) {
- msr.hi &= ~(0x3 << (36 - 32)); /* ThrottleNbInterface[3:2] */
- msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32));
- }
- msr.lo &= ~(0x3 << 6); /* ThrottleNbInterface[1:0] */
- msr.lo |= (((core_count - 1) & 0x3) << 6);
- msr.lo &= ~(0x1 << 24); /* WcPlusDis = 0 */
- wrmsr(BU_CFG2_MSR, msr);
- }
-
- /* Disable Cf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
- if (is_fam15h()) {
- msr = rdmsr(BU_CFG3_MSR);
- /* Set CombineCr0Cd */
- msr.hi |= (1 << (49-32));
- wrmsr(BU_CFG3_MSR, msr);
- } else {
- msr = rdmsr(BU_CFG2_MSR);
- /* Clear ClLinesToNbDis */
- msr.lo &= ~(1 << 15);
- /* Clear bit 35 as per Erratum 343 */
- msr.hi &= ~(1 << (35-32));
- wrmsr(BU_CFG2_MSR, msr);
- }
-
- if (CONFIG(HAVE_SMI_HANDLER)) {
- printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
-
- /* Set SMM base address for this CPU */
- msr = rdmsr(SMM_BASE_MSR);
- msr.lo = SMM_BASE - (lapicid() * 0x400);
- wrmsr(SMM_BASE_MSR, msr);
-
- /* Enable the SMM memory window */
- msr = rdmsr(SMM_MASK_MSR);
- msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
- wrmsr(SMM_MASK_MSR, msr);
- } else {
- printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
-
- /* Set SMM base address for this CPU */
- msr = rdmsr(SMM_BASE_MSR);
- msr.lo = SMM_BASE - (lapicid() * 0x400);
- wrmsr(SMM_BASE_MSR, msr);
-
- /* Disable the SMM memory window */
- msr.hi = 0x0;
- msr.lo = 0x0;
- wrmsr(SMM_MASK_MSR, msr);
- }
-
- /* Set SMMLOCK to avoid exploits messing with SMM */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
-
- fam15h_startup_flags[id.nodeid][id.coreid] = 1;
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = model_10xxx_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
-//AMD_GH_SUPPORT
- { X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
- { X86_VENDOR_AMD, 0x100f10 }, /* M2 */
- { X86_VENDOR_AMD, 0x100f20 }, /* S1g1 */
- { X86_VENDOR_AMD, 0x100f21 },
- { X86_VENDOR_AMD, 0x100f2A },
- { X86_VENDOR_AMD, 0x100f22 },
- { X86_VENDOR_AMD, 0x100f23 },
- { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
- { X86_VENDOR_AMD, 0x100f42 }, /* RB-C2 */
- { X86_VENDOR_AMD, 0x100f43 }, /* RB-C3 */
- { X86_VENDOR_AMD, 0x100f52 }, /* BL-C2 */
- { X86_VENDOR_AMD, 0x100f62 }, /* DA-C2 */
- { X86_VENDOR_AMD, 0x100f63 }, /* DA-C3 */
- { X86_VENDOR_AMD, 0x100f80 }, /* HY-D0 */
- { X86_VENDOR_AMD, 0x100f81 }, /* HY-D1 */
- { X86_VENDOR_AMD, 0x100f91 }, /* HY-D1 */
- { X86_VENDOR_AMD, 0x100fa0 }, /* PH-E0 */
- { X86_VENDOR_AMD, 0x600f12 }, /* OR-B2 */
- { X86_VENDOR_AMD, 0x600f20 }, /* OR-C0 */
- { 0, 0 },
-};
-
-static const struct cpu_driver model_10xxx __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
deleted file mode 100644
index 51244b8..0000000
--- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <timer.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <northbridge/amd/amdht/AsPsDefs.h>
-
-static struct monotonic_counter {
- int initialized;
- uint32_t core_frequency;
- struct mono_time time;
- uint64_t last_value;
-} mono_counter;
-
-static inline uint64_t read_counter_msr(void)
-{
- msr_t counter_msr;
-
- counter_msr = rdmsr(TSC_MSR);
-
- return ((uint64_t)counter_msr.hi << 32) | (uint64_t)counter_msr.lo;
-}
-
-static void init_timer(void)
-{
- uint8_t model;
- uint32_t cpuid_fms;
- uint8_t cpufid;
- uint8_t cpudid;
- uint8_t boost_capable = 0;
-
- /* Get CPU model */
- cpuid_fms = cpuid_eax(0x80000001);
- model = ((cpuid_fms & 0xf0000) >> 16) | ((cpuid_fms & 0xf0) >> 4);
-
- /* Get boost capability */
- if ((model == 0x8) || (model == 0x9)) { /* revision D */
- boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4),
- 0x15c) & 0x4) >> 2;
- }
-
- /* Set up TSC (BKDG v3.62 section 2.9.4)*/
- msr_t msr = rdmsr(HWCR_MSR);
- msr.lo |= 0x1000000;
- wrmsr(HWCR_MSR, msr);
-
- /* Get core Pstate 0 frequency in MHz */
- msr = rdmsr(PSTATE_0_MSR + boost_capable);
- cpufid = (msr.lo & 0x3f);
- cpudid = (msr.lo & 0x1c0) >> 6;
- mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
-
- mono_counter.last_value = read_counter_msr();
- mono_counter.initialized = 1;
-}
-
-void timer_monotonic_get(struct mono_time *mt)
-{
- uint64_t current_tick;
- uint32_t usecs_elapsed = 0;
-
- if (!mono_counter.initialized)
- init_timer();
-
- current_tick = read_counter_msr();
- if (mono_counter.core_frequency != 0)
- usecs_elapsed = (current_tick - mono_counter.last_value) / mono_counter.core_frequency;
-
- /* Update current time and tick values only if a full tick occurred. */
- if (usecs_elapsed) {
- mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
- mono_counter.last_value = current_tick;
- }
-
- /* Save result. */
- *mt = mono_counter.time;
-}
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
deleted file mode 100644
index 4029f72..0000000
--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <option.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <arch/acpigen.h>
-#include <cpu/amd/powernow.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-#include <arch/cpu.h>
-#include <northbridge/amd/amdht/AsPsDefs.h>
-#include <northbridge/amd/amdmct/mct/mct.h>
-#include <northbridge/amd/amdmct/amddefs.h>
-#include <types.h>
-
-static inline uint8_t is_fam15h(void)
-{
- uint8_t fam15h = 0;
- uint32_t family;
-
- family = cpuid_eax(0x80000001);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f)
- /* Family 15h or later */
- fam15h = 1;
-
- return fam15h;
-}
-
-static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power,
- u32 *pstate_latency, u32 *pstate_control,
- u32 *pstate_status, int coreID,
- uint8_t single_link)
-{
- int i;
- struct cpuid_result cpuid1;
-
- acpigen_write_empty_PCT();
- acpigen_write_name("_PSS");
-
- /* add later to total sum */
- acpigen_write_package(pstate_num);
-
- for (i = 0;i < pstate_num; i++)
- acpigen_write_PSS_package(pstate_feq[i],
- pstate_power[i],
- pstate_latency[i],
- pstate_latency[i],
- pstate_control[i],
- pstate_status[i]);
-
- /* update the package size */
- acpigen_pop_len();
-
- /* Write PPC object */
- acpigen_write_PPC(pstate_num);
-
- /* Write PSD indicating coordination type */
- if ((single_link) && (mctGetLogicalCPUID(0) & AMD_DR_GT_Bx)) {
- /* Revision C or greater single-link processor */
- cpuid1 = cpuid(0x80000008);
- acpigen_write_PSD_package(0, (cpuid1.ecx & 0xff) + 1, SW_ALL);
- } else {
- /* Find the local APIC ID for the specified core ID */
- struct device* cpu;
- int cpu_index = 0;
- for (cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
- continue;
- if (!cpu->enabled)
- continue;
- if (cpu_index == coreID)
- break;
- cpu_index++;
- }
-
- if (cpu)
- acpigen_write_PSD_package(cpu->path.apic.apic_id, 1, SW_ANY);
- }
-}
-
-static void write_cstates_for_core(int coreID)
-{
- /* Generate C state entries */
- uint8_t cstate_count = 1;
- acpi_cstate_t cstate;
-
- if (is_fam15h()) {
- cstate.ctype = 2;
- cstate.latency = 100;
- cstate.power = 0;
- cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO;
- cstate.resource.bit_width = 8;
- cstate.resource.bit_offset = 0;
- cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1;
- cstate.resource.addrh = 0;
- cstate.resource.access_size = 1;
- } else {
- cstate.ctype = 2;
- cstate.latency = 75;
- cstate.power = 0;
- cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO;
- cstate.resource.bit_width = 8;
- cstate.resource.bit_offset = 0;
- cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo;
- cstate.resource.addrh = 0;
- cstate.resource.access_size = 1;
- }
-
- acpigen_write_CST_package(&cstate, cstate_count);
-
- /* Find the local APIC ID for the specified core ID */
- if (is_fam15h()) {
- struct device* cpu;
- int cpu_index = 0;
- for (cpu = all_devices; cpu; cpu = cpu->next) {
- if ((cpu->path.type != DEVICE_PATH_APIC) ||
- (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER))
- continue;
- if (!cpu->enabled)
- continue;
- if (cpu_index == coreID)
- break;
- cpu_index++;
- }
-
- if (cpu) {
- /* TODO
- * Detect dual core status and skip CSD generation if dual core is disabled
- */
-
- /* Generate C state dependency entries */
- acpigen_write_CSD_package((cpu->path.apic.apic_id >> 1) & 0x7f, 2, CSD_HW_ALL, 0);
- }
- }
-}
-
-/*
-* For details of this algorithm, please refer to:
-* Family 10h BDKG 3.62 page 69
-* Family 15h BDKG 3.14 page 74
-*
-* WARNING: The core count algorithm below assumes that all processors
-* are identical, with the same number of active cores. While the BKDG
-* states the BIOS must enforce this coreboot does not currently do so.
-* As a result it is possible that this code may break if an illegal
-* processor combination is installed. If it does break please fix the
-* code in the proper locations!
-*/
-void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
-{
- u8 processor_brand[49];
- u32 *v;
- struct cpuid_result cpuid1;
-
- u16 Pstate_feq[10];
- u32 Pstate_power[10];
- u32 Pstate_latency[10];
- u32 Pstate_control[10];
- u32 Pstate_status[10];
- u8 Pstate_num;
- u8 cmp_cap;
- u8 index;
- msr_t msr;
-
- uint8_t nvram;
- uint8_t enable_c_states;
-
- enable_c_states = 0;
-#if CONFIG(HAVE_ACPI_TABLES)
- if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
- enable_c_states = !!nvram;
-#endif
-
- /* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
- cpuid1 = cpuid(0x80000002);
- v = (u32 *) processor_brand;
- v[0] = cpuid1.eax;
- v[1] = cpuid1.ebx;
- v[2] = cpuid1.ecx;
- v[3] = cpuid1.edx;
- cpuid1 = cpuid(0x80000003);
- v[4] = cpuid1.eax;
- v[5] = cpuid1.ebx;
- v[6] = cpuid1.ecx;
- v[7] = cpuid1.edx;
- cpuid1 = cpuid(0x80000004);
- v[8] = cpuid1.eax;
- v[9] = cpuid1.ebx;
- v[10] = cpuid1.ecx;
- v[11] = cpuid1.edx;
- processor_brand[48] = 0;
- printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
-
- uint32_t dtemp;
- uint8_t node_index;
- uint8_t node_count;
- uint8_t cores_per_node;
- uint8_t total_core_count;
- uint8_t fam15h;
- uint8_t fam10h_rev_e = 0;
-
- /* Detect Revision E processors via method used in fidvid.c */
- if ((cpuid_edx(0x80000007) & CPB_MASK)
- && ((cpuid_ecx(0x80000008) & NC_MASK) == 5))
- fam10h_rev_e = 1;
-
- /*
- * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit.
- * socket_type : 0x10 SocketF; 0x11 AM2/ASB1; 0x12 S1G1
- * cmp_cap : 0x0 SingleCore; 0x1 DualCore; 0x2 TripleCore; 0x3 QuadCore; 0x4 QuintupleCore; 0x5 HexCore
- */
- printk(BIOS_INFO, "Pstates algorithm ...\n");
- fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL);
- /* Get number of cores */
- if (fam15h) {
- cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) &
- 0xff;
- } else {
- dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8);
- cmp_cap = (dtemp & 0x3000) >> 12;
- if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL)) /* revision D or higher */
- cmp_cap |= (dtemp & 0x8000) >> 13;
- }
-
- /* Get number of nodes */
- dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60);
- node_count = ((dtemp & 0x70) >> 4) + 1;
- cores_per_node = cmp_cap + 1;
-
- /* Compute total number of cores installed in system */
- total_core_count = cores_per_node * node_count;
-
- /* Get number of boost states */
- uint8_t boost_count = 0;
- dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c);
- if (fam10h_rev_e)
- boost_count = (dtemp >> 2) & 0x1;
- else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL)
- boost_count = (dtemp >> 2) & 0x7;
-
- /* See if the CPUID(0x80000007) returned EDX[7]==1b */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x80) != 0x80) {
- printk(BIOS_INFO, "No valid set of P-states\n");
- return;
- }
-
- if (fam15h)
- /* Set P_LVL2 P_BLK entry */
- *(((uint8_t *)pcontrol_blk) + 0x04) =
- (rdmsr(MSR_CSTATE_ADDRESS).lo + 1) & 0xff;
-
- uint8_t pviModeFlag;
- uint8_t Pstate_max;
- uint8_t cpufid;
- uint8_t cpudid;
- uint8_t cpuvid;
- uint8_t cpuidd;
- uint8_t cpuidv;
- uint8_t power_step_up;
- uint8_t power_step_down;
- uint8_t pll_lock_time;
- uint32_t expanded_cpuidv;
- uint32_t core_frequency;
- uint32_t core_power;
- uint32_t core_latency;
- uint32_t core_voltage; /* multiplied by 10000 */
- uint8_t single_link;
-
- /* Determine if this is a PVI or SVI system */
- dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
-
- if (dtemp & PVI_MODE)
- pviModeFlag = 1;
- else
- pviModeFlag = 0;
-
- /* Get PSmax's index */
- msr = rdmsr(PS_LIM_REG);
- Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & ((fam15h)?BIT_MASK_7:BIT_MASK_3));
-
- /* Determine if all enabled Pstates have the same fidvid */
- uint8_t i;
- uint8_t cpufid_prev = (rdmsr(PSTATE_0_MSR).lo & 0x3f);
- uint8_t all_enabled_cores_have_same_cpufid = 1;
- for (i = 1; i < Pstate_max; i++) {
- cpufid = rdmsr(PSTATE_0_MSR + i).lo & 0x3f;
- if (cpufid != cpufid_prev) {
- all_enabled_cores_have_same_cpufid = 0;
- break;
- }
- }
-
- /* Family 15h uses slightly different PSmax numbering */
- if (fam15h)
- Pstate_max++;
-
- /* Populate tables with all Pstate information */
- for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) {
- /* Get power state information */
- msr = rdmsr(PSTATE_0_MSR + Pstate_num + boost_count);
- cpufid = (msr.lo & 0x3f);
- cpudid = (msr.lo & 0x1c0) >> 6;
- cpuvid = (msr.lo & 0xfe00) >> 9;
- cpuidd = (msr.hi & 0xff);
- cpuidv = (msr.hi & 0x300) >> 8;
- core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);
- if (pviModeFlag) {
- if (cpuvid >= 0x20) {
- core_voltage = 7625 - (((cpuvid - 0x20) * 10000) / 80);
- } else {
- core_voltage = 15500 - ((cpuvid * 10000) / 40);
- }
- } else {
- cpuvid = cpuvid & 0x7f;
- if (cpuvid >= 0x7c)
- core_voltage = 0;
- else
- core_voltage = 15500 - ((cpuvid * 10000) / 80);
- }
- switch (cpuidv) {
- case 0x0:
- expanded_cpuidv = 1;
- break;
- case 0x1:
- expanded_cpuidv = 10;
- break;
- case 0x2:
- expanded_cpuidv = 100;
- break;
- case 0x3:
- expanded_cpuidv = 1000;
- break;
- default:
- printk(BIOS_ERR, "%s:%s:%d: Invalid cpuidv, "
- "not generating pstate tables.\n",
- __FILE__, __func__, __LINE__);
- return;
- }
- core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);
-
- /* Calculate transition latency */
- dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4);
- power_step_up = (dtemp & 0xf000000) >> 24;
- power_step_down = (dtemp & 0xf00000) >> 20;
- dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
- pll_lock_time = (dtemp & 0x3800) >> 11;
- if (all_enabled_cores_have_same_cpufid)
- core_latency = ((12 * power_step_down) + power_step_up) / 1000;
- else
- core_latency = (12 * (power_step_down + power_step_up) / 1000)
- + pll_lock_time;
-
- Pstate_feq[Pstate_num] = core_frequency;
- Pstate_power[Pstate_num] = core_power;
- Pstate_latency[Pstate_num] = core_latency;
- Pstate_control[Pstate_num] = Pstate_num;
- Pstate_status[Pstate_num] = Pstate_num;
- }
-
- /* Print Pstate frequency, power, and latency */
- for (index = 0; index < Pstate_num; index++) {
- printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
- Pstate_feq[index]);
- printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
- Pstate_power[index]);
- printk(BIOS_INFO, "Pstate_latency[%d] = %dus\n", index,
- Pstate_latency[index]);
- }
-
- /* Enter processor block scope */
- char pscope[] = "\\_PR";
- acpigen_write_scope(pscope);
-
- for (index = 0; index < total_core_count; index++) {
- /* Determine if this is a single-link processor */
- node_index = 0x18 + (index / cores_per_node);
- dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80);
- single_link = !!(((dtemp & 0xff00) >> 8) == 0);
-
- /* Enter processor core scope */
- uint8_t plen_cur = plen;
- uint32_t pcontrol_blk_cur = pcontrol_blk;
- if ((onlyBSP) && (index != 0)) {
- plen_cur = 0;
- pcontrol_blk_cur = 0;
- }
- acpigen_write_processor(index, pcontrol_blk_cur, plen_cur);
-
- /* Write P-state status and dependency objects */
- write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
- Pstate_latency, Pstate_control, Pstate_status,
- index, single_link);
-
- /* Write C-state status and dependency objects */
- if (fam15h && enable_c_states)
- write_cstates_for_core(index);
-
- /* Exit processor core scope */
- acpigen_pop_len();
- }
-
- /* Exit processor block scope */
- acpigen_pop_len();
-}
-
-void amd_powernow_update_fadt(acpi_fadt_t * fadt)
-{
- if (is_fam15h()) {
- fadt->p_lvl2_lat = 101; /* NOTE: While the BKDG states this should
- * be set to 100, there is no way to meet
- * the other FADT requirements. I suspect
- * there is an error in the BKDG for ACPI
- * 1.x support; disable all FADT-based C
- * states > 2... */
- fadt->p_lvl3_lat = 1001;
- fadt->flags |= 0x1 << 2; /* FLAGS.PROC_C1 = 1 */
- fadt->flags |= 0x1 << 3; /* FLAGS.P_LVL2_UP = 1 */
- } else {
- fadt->cst_cnt = 0;
- }
- fadt->pstate_cnt = 0;
-}
diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c
deleted file mode 100644
index c5e31fd..0000000
--- a/src/cpu/amd/family_10h-family_15h/processor_name.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * This code sets the Processor Name String for AMD64 CPUs.
- *
- * Revision Guide for AMD Family 10h Processors
- * Publication # 41322 Revision: 3.17 Issue Date: February 2008
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pnp.h>
-#include <device/pci_ops.h>
-#include <stdlib.h>
-#include <types.h>
-
-/* The maximum length of CPU names is 48 bytes, including the final NULL byte.
- * If you change these names your BIOS will _NOT_ pass the AMD validation and
- * your mainboard will not be posted on the AMD Recommended Motherboard Website
- */
-
-struct str_s {
- u8 Pg;
- u8 NC;
- u8 String;
- char const *value;
-};
-
-
-static const struct str_s String1_socket_F[] = {
- {0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 83"},
- {0x00, 0x01, 0x01, "Dual-Core AMD Opteron(tm) Processor 23"},
- {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 83"},
- {0x00, 0x03, 0x01, "Quad-Core AMD Opteron(tm) Processor 23"},
- {0x00, 0x05, 0x00, "Six-Core AMD Opteron(tm) Processor 84"},
- {0x00, 0x05, 0x01, "Six-Core AMD Opteron(tm) Processor 24"},
- {0x00, 0x03, 0x02, "Embedded AMD Opteron(tm) Processor 83"},
- {0x00, 0x03, 0x03, "Embedded AMD Opteron(tm) Processor 23"},
- {0x00, 0x03, 0x04, "Embedded AMD Opteron(tm) Processor 13"},
- {0x00, 0x03, 0x05, "AMD Phenom(tm) FX-"},
- {0x01, 0x01, 0x01, "Embedded AMD Opteron(tm) Processor"},
- {0, 0, 0, NULL}
-};
-
-static const struct str_s String2_socket_F[] = {
- {0x00, 0xFF, 0x02, " EE"},
- {0x00, 0xFF, 0x0A, " SE"},
- {0x00, 0xFF, 0x0B, " HE"},
- {0x00, 0xFF, 0x0C, " EE"},
- {0x00, 0xFF, 0x0D, " Quad-Core Processor"},
- {0x00, 0xFF, 0x0F, ""},
- {0x01, 0x01, 0x01, "GF HE"},
- {0, 0, 0, NULL}
-};
-
-
-static const struct str_s String1_socket_AM2[] = {
- {0x00, 0x00, 0x00, "AMD Athlon(tm) Processor LE-"},
- {0x00, 0x00, 0x01, "AMD Sempron(tm) Processor LE-"},
- {0x00, 0x00, 0x02, "AMD Sempron(tm) 1"},
- {0x00, 0x00, 0x03, "AMD Athlon(tm) II 1"},
- {0x00, 0x01, 0x00, "Dual-Core AMD Opteron(tm) Processor 13"},
- {0x00, 0x01, 0x01, "AMD Athlon(tm)"},
- {0x00, 0x01, 0x03, "AMD Athlon(tm) II X2 2"},
- {0x00, 0x01, 0x04, "AMD Athlon(tm) II X2 B"},
- {0x00, 0x01, 0x05, "AMD Athlon(tm) II X2"},
- {0x00, 0x01, 0x07, "AMD Phenom(tm) II X2 5"},
- {0x00, 0x01, 0x0A, "AMD Phenom(tm) II X2"},
- {0x00, 0x01, 0x0B, "AMD Phenom(tm) II X2 B"},
- {0x00, 0x02, 0x00, "AMD Phenom(tm)"},
- {0x00, 0x02, 0x03, "AMD Phenom(tm) II X3 B"},
- {0x00, 0x02, 0x04, "AMD Phenom(tm) II X3"},
- {0x00, 0x02, 0x07, "AMD Athlon(tm) II X3 4"},
- {0x00, 0x02, 0x08, "AMD Phenom(tm) II X3 7"},
- {0x00, 0x02, 0x0A, "AMD Athlon(tm) II X3"},
- {0x00, 0x03, 0x00, "Quad-Core AMD Opteron(tm) Processor 13"},
- {0x00, 0x03, 0x01, "AMD Phenom(tm) FX-"},
- {0x00, 0x03, 0x02, "AMD Phenom(tm)"},
- {0x00, 0x03, 0x03, "AMD Phenom(tm) II X4 9"},
- {0x00, 0x03, 0x04, "AMD Phenom(tm) II X4 8"},
- {0x00, 0x03, 0x07, "AMD Phenom(tm) II X4 B"},
- {0x00, 0x03, 0x08, "AMD Phenom(tm) II X4"},
- {0x00, 0x03, 0x0A, "AMD Athlon(tm) II X4 6"},
- {0x00, 0x03, 0x0F, "AMD Athlon(tm) II X4"},
- {0, 0, 0, NULL}
-};
-
-static const struct str_s String2_socket_AM2[] = {
- {0x00, 0x00, 0x00, "00"},
- {0x00, 0x00, 0x01, "10"},
- {0x00, 0x00, 0x02, "20"},
- {0x00, 0x00, 0x03, "30"},
- {0x00, 0x00, 0x04, "40"},
- {0x00, 0x00, 0x05, "50"},
- {0x00, 0x00, 0x06, "60"},
- {0x00, 0x00, 0x07, "70"},
- {0x00, 0x00, 0x08, "80"},
- {0x00, 0x00, 0x09, "90"},
- {0x00, 0x00, 0x09, " Processor"},
- {0x00, 0x00, 0x09, "u Processor"},
- {0x00, 0x01, 0x00, "00 Dual-Core Processor"},
- {0x00, 0x01, 0x01, "00e Dual-Core Processor"},
- {0x00, 0x01, 0x02, "00B Dual-Core Processor"},
- {0x00, 0x01, 0x03, "50 Dual-Core Processor"},
- {0x00, 0x01, 0x04, "50e Dual-Core Processor"},
- {0x00, 0x01, 0x05, "50B Dual-Core Processor"},
- {0x00, 0x01, 0x06, " Processor"},
- {0x00, 0x01, 0x07, "e Processor"},
- {0x00, 0x01, 0x09, "0 Processor"},
- {0x00, 0x01, 0x0A, "0e Processor"},
- {0x00, 0x01, 0x0B, "u Processor"},
- {0x00, 0x02, 0x00, "00 Triple-Core Processor"},
- {0x00, 0x02, 0x01, "00e Triple-Core Processor"},
- {0x00, 0x02, 0x02, "00B Triple-Core Processor"},
- {0x00, 0x02, 0x03, "50 Triple-Core Processor"},
- {0x00, 0x02, 0x04, "50e Triple-Core Processor"},
- {0x00, 0x02, 0x05, "50B Triple-Core Processor"},
- {0x00, 0x02, 0x06, " Processor"},
- {0x00, 0x02, 0x07, "e Processor"},
- {0x00, 0x02, 0x09, "0e Processor"},
- {0x00, 0x02, 0x0A, "0 Processor"},
- {0x00, 0x03, 0x00, "00 Quad-Core Processor"},
- {0x00, 0x03, 0x01, "00e Quad-Core Processor"},
- {0x00, 0x03, 0x02, "00B Quad-Core Processor"},
- {0x00, 0x03, 0x03, "50 Quad-Core Processor"},
- {0x00, 0x03, 0x04, "50e Quad-Core Processor"},
- {0x00, 0x03, 0x05, "50B Quad-Core Processor"},
- {0x00, 0x03, 0x06, " Processor"},
- {0x00, 0x03, 0x07, "e Processor"},
- {0x00, 0x03, 0x09, "0e Processor"},
- {0x00, 0x03, 0x0A, " SE"},
- {0x00, 0x03, 0x0B, " HE"},
- {0x00, 0x03, 0x0C, " EE"},
- {0x00, 0x03, 0x0D, " Quad-Core Processor"},
- {0x00, 0x03, 0x0E, "0 Processor"},
- {0x00, 0xFF, 0x0F, ""},
- {0, 0, 0, NULL}
-};
-
-static const struct str_s String1_socket_G34[] = {
- {0x00, 0x07, 0x00, "AMD Opteron(tm) Processor 61"},
- {0x00, 0x0B, 0x00, "AMD Opteron(tm) Processor 61"},
- {0x01, 0x07, 0x01, "Embedded AMD Opteron(tm) Processor "},
- {0, 0, 0, NULL}
-};
-
-static const struct str_s String2_socket_G34[] = {
- {0x00, 0x07, 0x00, " HE"},
- {0x00, 0x07, 0x01, " SE"},
- {0x00, 0x0B, 0x00, " HE"},
- {0x00, 0x0B, 0x01, " SE"},
- {0x00, 0x0B, 0x0F, ""},
- {0x01, 0x07, 0x01, " QS"},
- {0x01, 0x07, 0x02, " KS"},
- {0, 0, 0, NULL}
-};
-
-static const struct str_s String1_socket_C32[] = {
- {0x00, 0x03, 0x00, "AMD Opteron(tm) Processor 41"},
- {0x00, 0x05, 0x00, "AMD Opteron(tm) Processor 41"},
- {0x01, 0x03, 0x01, "Embedded AMD Opteron(tm) Processor "},
- {0x01, 0x05, 0x01, "Embedded AMD Opteron(tm) Processor "},
- {0, 0, 0, NULL}
-};
-
-static const struct str_s String2_socket_C32[] = {
- {0x00, 0x03, 0x00, " HE"},
- {0x00, 0x03, 0x01, " EE"},
- {0x00, 0x05, 0x00, " HE"},
- {0x00, 0x05, 0x01, " EE"},
- {0x01, 0x03, 0x01, "QS HE"},
- {0x01, 0x03, 0x02, "LE HE"},
- {0x01, 0x05, 0x01, "KX HE"},
- {0x01, 0x05, 0x02, "GL EE"},
- {0, 0, 0, NULL}
-};
-
-const char *unknown = "AMD Processor model unknown";
-const char *unknown2 = " type unknown";
-const char *sample = "AMD Engineering Sample";
-const char *thermal = "AMD Thermal Test Kit";
-
-
-static int strcpymax(char *dst, const char *src, int buflen)
-{
- int i;
- for (i = 0; i < buflen && src[i]; i++)
- dst[i] = src[i];
- if (i >= buflen)
- i--;
- dst[i] = 0;
- return i;
-}
-
-#define NAME_STRING_MAXLEN 48
-
-int init_processor_name(void)
-{
- msr_t msr;
- ssize_t i;
- char program_string[NAME_STRING_MAXLEN];
- u32 *p_program_string = (u32 *)program_string;
- uint8_t fam15h = 0;
- uint32_t family;
-
- family = cpuid_eax(0x80000001);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f)
- /* Family 15h or later */
- fam15h = 1;
-
- /* null the string */
- memset(program_string, 0, sizeof(program_string));
-
- if (fam15h) {
- /* Family 15h or later */
- uint32_t dword;
- struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5);
- pci_write_config32(cpu_fn5_dev, 0x194, 0);
- dword = pci_read_config32(cpu_fn5_dev, 0x198);
- if (dword == 0) {
- strcpymax(program_string, sample, sizeof(program_string));
- } else {
- /* Assemble the string from PCI configuration register contents */
- for (i = 0; i < 12; i++) {
- pci_write_config32(cpu_fn5_dev, 0x194, i);
- p_program_string[i] = pci_read_config32(cpu_fn5_dev, 0x198);
- }
-
- /* Correctly place the null terminator */
- for (i = (NAME_STRING_MAXLEN - 2); i > 0; i--) {
- if (program_string[i] != 0x20)
- break;
- }
- program_string[i + 1] = 0;
- }
- } else {
- /* variable names taken from fam10 revision guide for clarity */
- u32 BrandId; /* CPUID Fn8000_0001_EBX */
- u8 String1; /* BrandID[14:11] */
- u8 String2; /* BrandID[3:0] */
- u8 Model; /* BrandID[10:4] */
- u8 Pg; /* BrandID[15] */
- u8 PkgTyp; /* BrandID[31:28] */
- u8 NC; /* CPUID Fn8000_0008_ECX */
- const char *processor_name_string = unknown;
- int j = 0, str2_checkNC = 1;
- const struct str_s *str, *str2;
-
- /* Find out which CPU brand it is */
- BrandId = cpuid_ebx(0x80000001);
- String1 = (u8)((BrandId >> 11) & 0x0F);
- String2 = (u8)((BrandId >> 0) & 0x0F);
- Model = (u8)((BrandId >> 4) & 0x7F);
- Pg = (u8)((BrandId >> 15) & 0x01);
- PkgTyp = (u8)((BrandId >> 28) & 0x0F);
- NC = (u8)(cpuid_ecx(0x80000008) & 0xFF);
-
- if (!Model) {
- processor_name_string = Pg ? thermal : sample;
- goto done;
- }
-
- switch (PkgTyp) {
- case 0: /* F1207 */
- str = String1_socket_F;
- str2 = String2_socket_F;
- str2_checkNC = 0;
- break;
- case 1: /* AM2 */
- str = String1_socket_AM2;
- str2 = String2_socket_AM2;
- break;
- case 3: /* G34 */
- str = String1_socket_G34;
- str2 = String2_socket_G34;
- str2_checkNC = 0;
- break;
- case 5: /* C32 */
- str = String1_socket_C32;
- str2 = String2_socket_C32;
- break;
- default:
- goto done;
- }
-
- /* String1 */
- for (i = 0; str[i].value; i++) {
- if ((str[i].Pg == Pg) &&
- (str[i].NC == NC) &&
- (str[i].String == String1)) {
- processor_name_string = str[i].value;
- break;
- }
- }
-
- if (!str[i].value)
- goto done;
-
- j = strcpymax(program_string, processor_name_string,
- sizeof(program_string));
-
- /* Translate Model from 01-99 to ASCII and put it on the end.
- * Numbers less than 10 should include a leading zero, e.g., 09.*/
- if (Model < 100 && j < sizeof(program_string) - 2) {
- program_string[j++] = (Model / 10) + '0';
- program_string[j++] = (Model % 10) + '0';
- }
-
- processor_name_string = unknown2;
-
- /* String 2 */
- for (i = 0; str2[i].value; i++) {
- if ((str2[i].Pg == Pg) &&
- ((str2[i].NC == NC) || !str2_checkNC) &&
- (str2[i].String == String2)) {
- processor_name_string = str2[i].value;
- break;
- }
- }
-
-done:
- strcpymax(&program_string[j], processor_name_string,
- sizeof(program_string) - j);
- }
-
- printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
-
- for (i = 0; i < 6; i++) {
- msr.lo = p_program_string[(2 * i) + 0];
- msr.hi = p_program_string[(2 * i) + 1];
- wrmsr_amd(0xC0010030 + i, msr);
- }
-
- return 0;
-}
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
deleted file mode 100644
index a1dc1f4..0000000
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cpu.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-
-#include <device/pci_ops.h>
-#include <device/device.h>
-#include <device/pci.h>
-
-#include <cbmem.h>
-
-#include "ram_calc.h"
-
-static inline uint8_t is_fam15h(void)
-{
- uint8_t fam15h = 0;
- uint32_t family;
-
- family = cpuid_eax(0x80000001);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f)
- /* Family 15h or later */
- fam15h = 1;
-
- return fam15h;
-}
-
-uint64_t get_uma_memory_size(uint64_t topmem)
-{
- uint64_t uma_size = 0;
- if (CONFIG(GFXUMA)) {
- /* refer to UMA Size Consideration in 780 BDG. */
- if (topmem >= 0x40000000) /* 1GB and above system memory */
- uma_size = 0x10000000; /* 256M recommended UMA */
-
- else if (topmem >= 0x20000000) /* 512M - 1023M system memory */
- uma_size = 0x8000000; /* 128M recommended UMA */
-
- else if (topmem >= 0x10000000) /* 256M - 511M system memory */
- uma_size = 0x4000000; /* 64M recommended UMA */
- }
-
- return uma_size;
-}
-
-uint64_t get_cc6_memory_size()
-{
- uint8_t enable_cc6;
-
- uint64_t cc6_size = 0;
-
- if (is_fam15h()) {
- enable_cc6 = 0;
-
-#if ENV_PCI_SIMPLE_DEVICE
- if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
- enable_cc6 = 1;
-#else
- struct device *dct_dev = pcidev_on_root(0x18, 2);
- if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18))
- enable_cc6 = 1;
-#endif
-
- if (enable_cc6) {
- /* Preserve the maximum possible CC6 save region
- * This needs to be kept in sync with
- * amdfam10_domain_read_resources() in northbridge.c
- */
- cc6_size = 0x8000000;
- }
- }
-
- return cc6_size;
-}
-
-void *cbmem_top_chipset(void)
-{
- uint32_t topmem = rdmsr(TOP_MEM).lo;
-
- return (void *) topmem - get_uma_memory_size(topmem) - get_cc6_memory_size();
-}
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.h b/src/cpu/amd/family_10h-family_15h/ram_calc.h
deleted file mode 100644
index 2b541d0..0000000
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _AMD_MODEL_10XXX_RAM_CALC_H_
-#define _AMD_MODEL_10XXX_RAM_CALC_H_
-
-uint64_t get_uma_memory_size(uint64_t topmem);
-uint64_t get_cc6_memory_size(void);
-
-#endif
diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c
deleted file mode 100644
index 793cc1b..0000000
--- a/src/cpu/amd/family_10h-family_15h/tsc_freq.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/tsc.h>
-
-unsigned long tsc_freq_mhz(void)
-{
- msr_t msr;
- uint8_t cpufid;
- uint8_t cpudid;
-
- /* On Family 10h/15h CPUs the TSC increments
- * at the P0 clock rate. Read the P0 clock
- * frequency from the P0 MSR and convert
- * to MHz. See also the Family 15h BKDG
- * Rev. 3.14 page 569.
- */
- msr = rdmsr(PSTATE_0_MSR);
- cpufid = (msr.lo & 0x3f);
- cpudid = (msr.lo & 0x1c0) >> 6;
-
- return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
-}
diff --git a/src/cpu/amd/family_10h-family_15h/update_microcode.c b/src/cpu/amd/family_10h-family_15h/update_microcode.c
deleted file mode 100644
index 4a2db4e..0000000
--- a/src/cpu/amd/family_10h-family_15h/update_microcode.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <cpu/amd/microcode.h>
-
-struct id_mapping {
- uint32_t orig_id;
- uint16_t new_id;
-};
-
-static u16 get_equivalent_processor_rev_id(u32 orig_id) {
- static const struct id_mapping id_mapping_table[] = {
- /* Family 10h */
- { 0x100f00, 0x1000 },
- { 0x100f01, 0x1000 },
- { 0x100f02, 0x1000 },
- { 0x100f20, 0x1020 },
- { 0x100f21, 0x1020 }, /* DR-B1 */
- { 0x100f2A, 0x1020 }, /* DR-BA */
- { 0x100f22, 0x1022 }, /* DR-B2 */
- { 0x100f23, 0x1022 }, /* DR-B3 */
- { 0x100f42, 0x1041 }, /* RB-C2 */
- { 0x100f43, 0x1043 }, /* RB-C3 */
- { 0x100f52, 0x1041 }, /* BL-C2 */
- { 0x100f62, 0x1062 }, /* DA-C2 */
- { 0x100f63, 0x1043 }, /* DA-C3 */
- { 0x100f81, 0x1081 }, /* HY-D1 */
- { 0x100f91, 0x1081 }, /* HY-D1 */
- { 0x100fa0, 0x10A0 }, /* PH-E0 */
-
- /* Family 15h */
- { 0x600f12, 0x6012 }, /* OR-B2 */
- { 0x600f20, 0x6020 }, /* OR-C0 */
-
- /* Array terminator */
- { 0xffffff, 0x0000 },
- };
-
- u32 new_id;
- int i;
-
- new_id = 0;
-
- for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
- if (id_mapping_table[i].orig_id == orig_id) {
- new_id = id_mapping_table[i].new_id;
- break;
- }
- }
-
- return new_id;
-
-}
-
-void update_microcode(u32 cpu_deviceid)
-{
- u32 equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid);
- amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
-}
diff --git a/src/cpu/amd/quadcore/Makefile.inc b/src/cpu/amd/quadcore/Makefile.inc
deleted file mode 100644
index c390b4e..0000000
--- a/src/cpu/amd/quadcore/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-ramstage-y += amd_sibling.c
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
deleted file mode 100644
index ac637ff..0000000
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/lapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <smp/spinlock.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-extern struct device *get_node_pci(u32 nodeid, u32 fn);
-
-#if 0
-static int first_time = 1;
-#endif
-
-#include "quadcore_id.c"
-
-static u32 get_max_siblings(u32 nodes)
-{
- struct device *dev;
- u32 nodeid;
- u32 siblings = 0;
-
- //get max siblings from all the nodes
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- int j;
- dev = get_node_pci(nodeid, 3);
- j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
- if (siblings < j)
- siblings = j;
- }
-
- return siblings;
-}
-
-
-static void enable_apic_ext_id(u32 nodes)
-{
- struct device *dev;
- u32 nodeid;
-
- //enable APIC_EXIT_ID all the nodes
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- u32 val;
- dev = get_node_pci(nodeid, 0);
- val = pci_read_config32(dev, 0x68);
- val |= (1 << 17)|(1 << 18);
- pci_write_config32(dev, 0x68, val);
- }
-}
-
-
-u32 get_apicid_base(u32 ioapic_num)
-{
- u32 apicid_base;
- u32 siblings;
- u32 nb_cfg_54;
-
- u32 disable_siblings = !CONFIG(LOGICAL_CPUS);
-
- get_option(&disable_siblings, "multi_core");
-
- siblings = get_max_siblings(sysconf.nodes);
-
- if (sysconf.bsp_apicid > 0) {
- // IOAPIC could start from 0
- return 0;
- } else if (sysconf.enabled_apic_ext_id) {
- // enabled ext id but bsp = 0
- return 1;
- }
-
- nb_cfg_54 = read_nb_cfg_54();
-
-
- //Construct apicid_base
-
- if ((!disable_siblings) && (siblings > 0)) {
- /* for 8 way dual core, we will used up apicid 16:16, actually
- 16 is not allowed by current kernel and the kernel will try
- to get one that is small than 16 to make IOAPIC work. I don't
- know when the kernel can support 256 APIC id.
- (APIC_EXT_ID is enabled) */
-
- //4:10 for two way 8:12 for four way 16:16 for eight way
- //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes
- //for better consistency?
- apicid_base = nb_cfg_54 ? (siblings+1) * sysconf.nodes :
- 8 * siblings + sysconf.nodes;
-
- } else {
- apicid_base = sysconf.nodes;
- }
-
- if ((apicid_base+ioapic_num-1) > 0xf) {
- // We need to enable APIC EXT ID
- printk(BIOS_SPEW, "if the IOAPIC device doesn't support 256 APIC id,\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for IOAPIC\n");
- enable_apic_ext_id(sysconf.nodes);
- }
-
- return apicid_base;
-}
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
deleted file mode 100644
index 8125fb4..0000000
--- a/src/cpu/amd/quadcore/quadcore.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cpu.h>
-#include <console/console.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#if CONFIG(HAVE_OPTION_TABLE)
-#include "option_table.h"
-#endif
-
-#include "cpu/amd/quadcore/quadcore_id.c"
-
-u32 get_core_num_in_bsp(u32 nodeid)
-{
- u32 dword;
- if (is_fam15h()) {
- /* Family 15h moved CmpCap to F5x84 [7:0] */
- dword = pci_read_config32(NODE_PCI(nodeid, 5), 0x84);
- dword &= 0xff;
- } else {
- dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
- dword >>= 12;
- /* Bit 15 is CmpCap[2] since Revision D. */
- if ((cpuid_ecx(0x80000008) & 0xff) > 3)
- dword = ((dword & 8) >> 1) | (dword & 3);
- else
- dword &= 3;
- }
- return dword;
-}
-
-u8 set_apicid_cpuid_lo(void)
-{
- // set the NB_CFG[54]=1; why the OS will be happy with that ???
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
- wrmsr(NB_CFG_MSR, msr);
-
- return 1;
-}
-
-void real_start_other_core(uint32_t nodeid, uint32_t cores)
-{
- ssize_t i;
- uint32_t dword;
-
- printk(BIOS_DEBUG,
- "Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
-
- /* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
- accesses and error logging to core0 */
- dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
- dword |= 1 << 30; /* SyncFloodOnDramAdrParErr=1 */
- dword |= 1 << 27; /* NbMcaToMstCpuEn=1 */
- dword |= 1 << 21; /* SyncFloodOnAnyUcErr=1 */
- dword |= 1 << 20; /* SyncFloodOnWDT=1 */
- dword |= 1 << 2; /* SyncFloodOnDramUcEcc=1 */
- pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
- if (is_fam15h()) {
- uint32_t core_activation_flags = 0;
- uint32_t active_cores = 0;
-
- /* Set PCI_DEV(0, 0x18+nodeid, 0),
- * 0x1dc bits 7:1 to start cores
- */
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x1dc);
- for (i = 1; i < cores + 1; i++)
- core_activation_flags |= 1 << i;
- /* Start the first core of each compute unit */
- active_cores |= core_activation_flags & 0x55;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword
- | active_cores);
-
- /* Each core shares a single set of MTRR registers with
- * another core in the same compute unit, therefore, it
- * is important that one core in each CU starts in advance
- * of the other in order to avoid one core stomping all over
- * the other core's settings.
- */
-
- /* Wait for the first core of each compute unit to start... */
- for (i = 1; i < cores + 1; i++) {
- if (!(i & 0x1)) {
- uint32_t ap_apicid =
- get_boot_apic_id(nodeid, i);
- /* Timeout */
- wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP,
- F10_APSTATE_ASLEEP);
- }
- }
-
- /* Start the second core of each compute unit */
- active_cores |= core_activation_flags & 0xaa;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x1dc, dword |
- active_cores);
- } else {
- // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
- dword |= 1 << 5;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
-
- if (cores > 1) {
- dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
- for (i = 0; i < cores - 1; i++)
- dword |= 1 << i;
- pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
- }
- }
-}
-
-#if (!CONFIG(CPU_AMD_MODEL_10XXX))
-//it is running on core0 of node0
-static void start_other_cores(void)
-{
- u32 nodes;
- u32 nodeid;
-
- // disable multi_core
- if (read_option(multi_core, 0) != 0) {
- printk(BIOS_DEBUG, "Skip additional core init\n");
- return;
- }
-
- nodes = get_nodes();
-
- for (nodeid = 0; nodeid < nodes; nodeid++) {
- u32 cores = get_core_num_in_bsp(nodeid);
- printk(BIOS_DEBUG, "init node: %02x cores: %02x pass 1\n",
- nodeid, cores);
- if (cores > 0)
- real_start_other_core(nodeid, cores);
- }
-}
-#endif
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
deleted file mode 100644
index 7ec1bdb..0000000
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/cpu.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/multicore.h>
-#include <device/pci_ops.h>
-
-//called by bus_cpu_scan too
-u32 read_nb_cfg_54(void)
-{
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- return (msr.hi >> (54-32)) & 1;
-}
-
-u32 get_initial_apicid(void)
-{
- return (cpuid_ebx(1) >> 24) & 0xff;
-}
-
-/* Called by amd_siblings (ramstage) as well */
-struct node_core_id get_node_core_id(u32 nb_cfg_54)
-{
- struct node_core_id id;
- uint8_t apicid;
- uint8_t fam15h = 0;
- uint8_t rev_gte_d = 0;
- uint8_t dual_node = 0;
- uint32_t f3xe8;
- uint32_t family;
- uint32_t model;
-
-#if ENV_PCI_SIMPLE_DEVICE
- f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8);
-#else
- f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8);
-#endif
-
- family = model = cpuid_eax(0x80000001);
- model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f) {
- /* Family 15h or later */
- fam15h = 1;
- nb_cfg_54 = 1;
- }
-
- if ((model >= 0x8) || fam15h)
- /* Revision D or later */
- rev_gte_d = 1;
-
- if (rev_gte_d)
- /* Check for dual node capability */
- if (f3xe8 & 0x20000000)
- dual_node = 1;
-
- /* Get the apicid via cpuid(1) ebx[31:24]
- * The apicid format varies based on processor revision
- */
- apicid = (cpuid_ebx(1) >> 24) & 0xff;
- if (nb_cfg_54) {
- if (fam15h && dual_node) {
- id.coreid = apicid & 0x1f;
- id.nodeid = (apicid & 0x60) >> 5;
- } else if (fam15h && !dual_node) {
- id.coreid = apicid & 0xf;
- id.nodeid = (apicid & 0x70) >> 4;
- } else if (rev_gte_d && dual_node) {
- id.coreid = apicid & 0xf;
- id.nodeid = (apicid & 0x30) >> 4;
- } else if (rev_gte_d && !dual_node) {
- id.coreid = apicid & 0x7;
- id.nodeid = (apicid & 0x38) >> 3;
- } else {
- id.coreid = apicid & 0x3;
- id.nodeid = (apicid & 0x1c) >> 2;
- }
- } else {
- if (rev_gte_d && dual_node) {
- id.coreid = (apicid & 0xf0) >> 4;
- id.nodeid = apicid & 0x3;
- } else if (rev_gte_d && !dual_node) {
- id.coreid = (apicid & 0xe0) >> 5;
- id.nodeid = apicid & 0x7;
- } else {
- id.coreid = (apicid & 0x60) >> 5;
- id.nodeid = apicid & 0x7;
- }
- }
- if (fam15h && dual_node) {
- /* coreboot expects each separate processor die to be on a
- * different nodeid.
- * Since the code above returns nodeid 0 even on
- * internal node 1 some fixup is needed...
- */
- uint32_t f5x84;
- uint8_t core_count;
-
-#if ENV_PCI_SIMPLE_DEVICE
- f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84);
-#else
- f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84);
-#endif
- core_count = (f5x84 & 0xff) + 1;
- id.nodeid = id.nodeid * 2;
- if (id.coreid >= core_count) {
- id.nodeid += 1;
- id.coreid = id.coreid - core_count;
- }
- } else if (rev_gte_d && dual_node) {
- /* coreboot expects each separate processor die to be on a
- * different nodeid.
- * Since the code above returns nodeid 0 even on
- * internal node 1 some fixup is needed...
- */
- uint8_t core_count = (((f3xe8 & 0x00008000) >> 13) |
- ((f3xe8 & 0x00003000) >> 12)) + 1;
-
- id.nodeid = id.nodeid * 2;
- if (id.coreid >= core_count) {
- id.nodeid += 1;
- id.coreid = id.coreid - core_count;
- }
- }
-
- return id;
-}
-
-#ifdef UNUSED_CODE
-static u32 get_core_num(void)
-{
- return (cpuid_ecx(0x80000008) & 0xff);
-}
-#endif
-
-struct node_core_id get_node_core_id_x(void)
-{
- return get_node_core_id(read_nb_cfg_54());
-}
diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
deleted file mode 100644
index 60b11bf..0000000
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_AM2R2
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_AM2R2
-
-config CPU_SOCKET_TYPE
- hex
- default 0x11
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_AM2r2/Makefile.inc b/src/cpu/amd/socket_AM2r2/Makefile.inc
deleted file mode 100644
index 6917441..0000000
--- a/src/cpu/amd/socket_AM2r2/Makefile.inc
+++ /dev/null
@@ -1,13 +0,0 @@
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
deleted file mode 100644
index 4f61685..0000000
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_AM3
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_AM3
-
-config CPU_SOCKET_TYPE
- hex
- default 0x11
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_AM3/Makefile.inc b/src/cpu/amd/socket_AM3/Makefile.inc
deleted file mode 100644
index 6917441..0000000
--- a/src/cpu/amd/socket_AM3/Makefile.inc
+++ /dev/null
@@ -1,13 +0,0 @@
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
deleted file mode 100644
index 28779f5..0000000
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_ASB2
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_ASB2
-
-config CPU_SOCKET_TYPE
- hex
- default 0x13
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_ASB2/Makefile.inc b/src/cpu/amd/socket_ASB2/Makefile.inc
deleted file mode 100644
index 6917441..0000000
--- a/src/cpu/amd/socket_ASB2/Makefile.inc
+++ /dev/null
@@ -1,13 +0,0 @@
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
deleted file mode 100644
index 65d1cbb..0000000
--- a/src/cpu/amd/socket_C32/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_C32_NON_AGESA
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_C32_NON_AGESA
-
-config CPU_SOCKET_TYPE
- hex
- default 0x14
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc
deleted file mode 100644
index 6917441..0000000
--- a/src/cpu/amd/socket_C32/Makefile.inc
+++ /dev/null
@@ -1,13 +0,0 @@
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_FM2/Kconfig b/src/cpu/amd/socket_FM2/Kconfig
deleted file mode 100644
index a87694a..0000000
--- a/src/cpu/amd/socket_FM2/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_FM2_NON_AGESA
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_FM2_NON_AGESA
-
-config CPU_SOCKET_TYPE
- hex
- default 0x16
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_FM2/Makefile.inc b/src/cpu/amd/socket_FM2/Makefile.inc
deleted file mode 100644
index 6917441..0000000
--- a/src/cpu/amd/socket_FM2/Makefile.inc
+++ /dev/null
@@ -1,13 +0,0 @@
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
deleted file mode 100644
index c21ef55..0000000
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_F_1207
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_F_1207
-
-config CPU_SOCKET_TYPE
- hex
- default 0x10
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_F_1207/Makefile.inc b/src/cpu/amd/socket_F_1207/Makefile.inc
deleted file mode 100644
index ece8d9a..0000000
--- a/src/cpu/amd/socket_F_1207/Makefile.inc
+++ /dev/null
@@ -1,13 +0,0 @@
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_G34/Kconfig b/src/cpu/amd/socket_G34/Kconfig
deleted file mode 100644
index abc9726..0000000
--- a/src/cpu/amd/socket_G34/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config CPU_AMD_SOCKET_G34_NON_AGESA
- bool
- select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_SOCKET_G34_NON_AGESA
-
-config CPU_SOCKET_TYPE
- hex
- default 0x15
-
-config EXT_RT_TBL_SUPPORT
- bool
- default n
-
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
-config XIP_ROM_SIZE
- hex
- default 0x80000
-
-endif
diff --git a/src/cpu/amd/socket_G34/Makefile.inc b/src/cpu/amd/socket_G34/Makefile.inc
deleted file mode 100644
index de33cd3..0000000
--- a/src/cpu/amd/socket_G34/Makefile.inc
+++ /dev/null
@@ -1,14 +0,0 @@
-ramstage-y += socket_G34.c
-subdirs-y += ../family_10h-family_15h
-subdirs-y += ../quadcore
-subdirs-y += ../mtrr
-subdirs-y += ../microcode
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/pae
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/smm
-subdirs-y += ../smm
-
-cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc
diff --git a/src/cpu/amd/socket_G34/socket_G34.c b/src/cpu/amd/socket_G34/socket_G34.c
deleted file mode 100644
index 1cac37c..0000000
--- a/src/cpu/amd/socket_G34/socket_G34.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_socket_G34_ops = {
- CHIP_NAME("socket G34")
-};
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index ea6a41d..48350b3 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -142,9 +142,7 @@
}
return 0;
}
-#if !CONFIG(CPU_AMD_MODEL_10XXX)
mdelay(10);
-#endif
printk(BIOS_SPEW, "Deasserting INIT.\n");