soc/intel/common: Move L1_substates_control to pcie_rp.h
L1_substates_control is common define. Move out of soc level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 8e59c9a..f23b9d2 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/pcie_rp.h>
#include <soc/gpe.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
@@ -136,12 +137,7 @@
uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];
/* PCIe RP L1 substate */
- enum L1_substates_control {
- L1_SS_FSP_DEFAULT,
- L1_SS_DISABLED,
- L1_SS_L1_1,
- L1_SS_L1_2,
- } PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
+ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS];
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 578a600..2030e72 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -63,4 +63,12 @@
*/
uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
+/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */
+enum L1_substates_control {
+ L1_SS_FSP_DEFAULT,
+ L1_SS_DISABLED,
+ L1_SS_L1_1,
+ L1_SS_L1_2,
+};
+
#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 37237bb..1d97b36 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@@ -116,12 +117,7 @@
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
- enum L1_substates_control {
- L1_SS_FSP_DEFAULT,
- L1_SS_DISABLED,
- L1_SS_L1_1,
- L1_SS_L1_2,
- } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* SMBus */
uint8_t SmbusEnable;
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 3b81339..6e52efd 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@@ -114,12 +115,7 @@
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
- enum L1_substates_control {
- L1_SS_FSP_DEFAULT,
- L1_SS_DISABLED,
- L1_SS_L1_1,
- L1_SS_L1_2,
- } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* SMBus */
uint8_t SmbusEnable;
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 86e77da..d3062cc 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -7,6 +7,7 @@
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/pcie_rp.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
@@ -247,12 +248,7 @@
uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
- enum L1_substates_control {
- L1_SS_FSP_DEFAULT,
- L1_SS_DISABLED,
- L1_SS_L1_1,
- L1_SS_L1_2,
- } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
+ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];