This page describes how to run coreboot on the HiFive Unleashed development board from SiFive, the first RISC-V board on the market with enough resources to run a multiuser operating system.
For general setup instructions, please refer to the Getting Started Guide.
The following things are still missing from this coreboot port:
Run make menuconfig
and select SiFive/HiFive Unleashed in the Mainboard menu.
A total of 16 boot modes can be configured using the switches labeled MSEL0
through MSEL3
. The most important ones are as follows:
The HiFive Unleashed has an 32 MiB SPI flash (ISSI IS25WP256D), that can be programmed from within Linux running on the board, via USB/JTAG, or directly with an SPI programmer.
The SPI flash can be accessed as /dev/mtd0
from Linux.
To program the flash via USB/JTAG, connect the USB port to a computer. If the board is powered on, two new serial ports, for example /dev/ttyUSB0
and /dev/ttyUSB1
will appear. The first is JTAG, and the second is connected to the SoC's UART.
openocd -f openocd.cfg
>
:> flash write_image erase unlock build/coreboot.rom 0x20000000 auto erase enabled auto unlock enabled wrote 33554432 bytes from file build/coreboot.rom in 1524.943848s (21.488 KiB/s)
Note that programming the whole flash with OpenOCD isn't fast. In this example it took just over 25 minutes. This process can be sped up considerably by building/flashing a smaller image; OpenOCD does not check if the image and the flash have the same size.
External programming with an SPI adapter and flashrom may work, but has not been tested. Please study the schematics before going this route.
The zeroth-stage bootloader (ZSBL) in ROM1 can print error codes on the serial console in certain situations.
// Error codes are formatted as follows: // [63:60] [59:56] [55:0] // bootstage trap errorcode // If trap == 1, then errorcode is actually the mcause register with the // interrupt bit shifted to bit 55.
(--- from the SiFive forum)