diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 1f028c3..a53978d 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -164,28 +164,22 @@
 			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }
 
-static bool is_s0ix_enabled(void)
+static bool is_s0ix_enabled(const struct device *dev)
 {
 	if (!haswell_is_ult())
 		return false;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-
-	if (!lapic || !lapic->chip_info)
-		return false;
-
-	const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
+	const struct cpu_intel_haswell_config *conf = dev->chip_info;
 	return conf->s0ix_enable;
 }
 
-static void generate_C_state_entries(void)
+static void generate_C_state_entries(const struct device *dev)
 {
 	acpi_cstate_t acpi_cstate_map[3] = {0};
 
 	const int *acpi_cstates;
 
-	if (is_s0ix_enabled())
+	if (is_s0ix_enabled(dev))
 		acpi_cstates = cstate_set_s0ix;
 	else if (haswell_is_ult())
 		acpi_cstates = cstate_set_lp;
@@ -352,7 +346,7 @@
 				coreID - 1, cores_per_package);
 
 			/* Generate C-state tables */
-			generate_C_state_entries();
+			generate_C_state_entries(device);
 
 			/* Generate T-state tables */
 			generate_T_state_entries(
diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h
index 776e239..5f2324c 100644
--- a/src/cpu/intel/haswell/chip.h
+++ b/src/cpu/intel/haswell/chip.h
@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Magic value used to locate this chip in the device tree */
-#define SPEEDSTEP_APIC_MAGIC 0xACAC
-
 #include <stdbool.h>
 #include <stdint.h>
 
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 7b3f3ad..5a0b09d 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -172,18 +172,16 @@
 	return 0;
 }
 
+static struct device *cpu_cluster;
+
 static void initialize_vr_config(void)
 {
 	struct cpu_vr_config vr_config = { 0 };
 	msr_t msr;
 
-	const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-
-	if (lapic && lapic->chip_info) {
-		const struct cpu_intel_haswell_config *conf = lapic->chip_info;
-
-		vr_config = conf->vr_config;
-	}
+	/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
+	const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info;
+	vr_config = conf->vr_config;
 
 	printk(BIOS_DEBUG, "Initializing VR config.\n");
 
@@ -448,18 +446,12 @@
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }
 
-static void configure_thermal_target(void)
+static void configure_thermal_target(struct device *dev)
 {
-	struct cpu_intel_haswell_config *conf;
-	struct device *lapic;
+	/* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */
+	struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info;
 	msr_t msr;
 
-	/* Find pointer to CPU configuration */
-	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	if (!lapic || !lapic->chip_info)
-		return;
-	conf = lapic->chip_info;
-
 	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
@@ -551,7 +543,7 @@
 	configure_misc();
 
 	/* Thermal throttle activation offset */
-	configure_thermal_target();
+	configure_thermal_target(cpu);
 
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
@@ -638,6 +630,7 @@
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
+	cpu_cluster = cpu_bus->dev;
 	/* TODO: Handle mp_init_with_smm failure? */
 	mp_init_with_smm(cpu_bus, &mp_ops);
 }
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index 7667392..e9a9876 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -3,12 +3,8 @@
 	# This mainboard has VGA
 	register "gpu_ddi_e_connected" = "1"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
index 144c247..d84c471 100644
--- a/src/mainboard/asrock/h81m-hds/devicetree.cb
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -3,12 +3,8 @@
 chip northbridge/intel/haswell
 	register "gpu_ddi_e_connected" = "1"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 440efdf..2ded452 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -14,14 +14,10 @@
 
 	register "ec_present" = "true"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			register "s0ix_enable" = "1"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+		register "s0ix_enable" = "1"
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 75bf8ee..be96e95 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -11,13 +11,10 @@
 
 	register "dq_pins_interleaved" = "true"
 
-	device cpu_cluster 0 on
-		chip cpu/intel/haswell
-			register "s0ix_enable" = "0"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on end
 
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+		register "s0ix_enable" = "0"
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index cfb4812..3de469ec 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -12,19 +12,17 @@
 		.backlight_pwm_hz	= 200,
 	}"
 
-	device cpu_cluster 0 on
-		chip cpu/intel/haswell
-			# Disable S0ix for now
-			register "s0ix_enable" = "0"
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on end
 
-			register "vr_config" = "{
-				.slow_ramp_rate_set    = 3,
-				.slow_ramp_rate_enable = true,
-			}"
+		# Disable S0ix for now
+		register "s0ix_enable" = "0"
 
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+		register "vr_config" = "{
+			.slow_ramp_rate_set    = 3,
+			.slow_ramp_rate_enable = true,
+		}"
+
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 9704cc3..18ec581 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -13,13 +13,8 @@
 
 	register "usb_xhci_on_resume" = "true"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index fe09566..59cf071 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -11,12 +11,8 @@
 
 	register "dq_pins_interleaved" = "true"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index d09d7a1..0c1222c 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -15,13 +15,8 @@
 
 	register "usb_xhci_on_resume" = "true"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb
index ee3209a..6a8e919 100644
--- a/src/mainboard/hp/folio_9480m/devicetree.cb
+++ b/src/mainboard/hp/folio_9480m/devicetree.cb
@@ -13,12 +13,8 @@
 		.backlight_pwm_hz	= 200,
 	}"
 	register "usb_xhci_on_resume" = "true"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index d5b566d..3226170 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -11,13 +11,8 @@
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 0becbbf..3b3a975 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -9,12 +9,8 @@
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
index 85c484b..fc00734 100644
--- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
+++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb
@@ -13,12 +13,8 @@
 		.backlight_pwm_hz	= 220,
 	}"
 	register "ec_present" = "true"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
index ef4668c..292a30d 100644
--- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
+++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb
@@ -13,12 +13,8 @@
 		.backlight_pwm_hz	= 220,
 	}"
 	register "ec_present" = "true"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb
index 429269c..f72ed9f 100644
--- a/src/mainboard/msi/h81m-p33/devicetree.cb
+++ b/src/mainboard/msi/h81m-p33/devicetree.cb
@@ -2,12 +2,8 @@
 
 chip northbridge/intel/haswell
 	register "gpu_ddi_e_connected" = "1"
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops haswell_pci_domain_ops
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index ae98c9e..45350b6 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -20,12 +20,8 @@
 		.backlight_pwm_hz	= 200,
 	}"
 
-	device cpu_cluster 0 on
-		ops broadwell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
 	end
 	device domain 0 on
 		ops broadwell_pci_domain_ops
diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
index 959c3b8..8625daa 100644
--- a/src/mainboard/supermicro/x10slm-f/devicetree.cb
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -2,12 +2,8 @@
 
 chip northbridge/intel/haswell
 
-	device cpu_cluster 0 on
-		ops haswell_cpu_bus_ops
-		chip cpu/intel/haswell
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
+	chip cpu/intel/haswell
+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
 	end
 
 	device domain 0 on
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index e11eb1c..bcb2a0b 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -536,7 +536,6 @@
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= northbridge_init,
 	.final			= northbridge_final,
-	.acpi_fill_ssdt		= generate_cpu_entries,
 	.ops_pci		= &pci_dev_ops_pci,
 };
 
@@ -561,6 +560,7 @@
 	.read_resources   = noop_read_resources,
 	.set_resources    = noop_set_resources,
 	.init             = mp_cpu_bus_init,
+	.acpi_fill_ssdt   = generate_cpu_entries,
 };
 
 struct chip_operations northbridge_intel_haswell_ops = {
diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index bbde3d2..a01f7ec 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -398,7 +398,6 @@
 
 static struct device_operations systemagent_ops = {
 	.read_resources   = systemagent_read_resources,
-	.acpi_fill_ssdt   = generate_cpu_entries,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = systemagent_init,
@@ -432,6 +431,7 @@
 	.read_resources   = noop_read_resources,
 	.set_resources    = noop_set_resources,
 	.init             = mp_cpu_bus_init,
+	.acpi_fill_ssdt   = generate_cpu_entries,
 };
 
 static void broadwell_init_pre_device(void *chip_info)