diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index 06f80de..e411aa2 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -13,24 +13,16 @@
 #include <soc/iomap.h>
 #include <amdblocks/biosram.h>
 
-#if CONFIG(ACPI_BERT)
- #if CONFIG_SMM_TSEG_SIZE == 0x0
-  #define BERT_REGION_MAX_SIZE 0x100000
- #else
-  /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */
-  #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE
- #endif
-#else
- #define BERT_REGION_MAX_SIZE 0
-#endif
-
 void bert_reserved_region(void **start, size_t *size)
 {
-	if (CONFIG(ACPI_BERT))
-		*start = cbmem_top();
-	else
+	if (!CONFIG(ACPI_BERT)) {
 		*start = NULL;
-	*size = BERT_REGION_MAX_SIZE;
+		*size = 0;
+	} else {
+		*start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE);
+		*size = CONFIG_ACPI_BERT_SIZE;
+	}
+	printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size);
 }
 
 void *cbmem_top_chipset(void)
@@ -42,13 +34,12 @@
 
 	/* 8MB alignment to keep MTRR usage low */
 	return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
-			- CONFIG_SMM_TSEG_SIZE
-			- BERT_REGION_MAX_SIZE, 8*MiB);
+				  - CONFIG_SMM_TSEG_SIZE, 8*MiB);
 }
 
 static uintptr_t smm_region_start(void)
 {
-	return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE;
+	return (uintptr_t)cbmem_top();
 }
 
 static size_t smm_region_size(void)