diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index b48b3c3..6a51dae 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -144,7 +144,6 @@
 
 static void gma_func0_init(struct device *dev)
 {
-	u32 reg32;
 	u8 *mmio;
 	u8 edid_data_lvds[128];
 	struct edid edid_lvds;
@@ -152,16 +151,13 @@
 
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (gtt_res == NULL)
 		return;
 	mmio = res2mmio(gtt_res, 0, 0);
 
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 		/* PCI Init, will run VBIOS */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index fa67fe1..19341d4 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -458,21 +458,18 @@
 static void gma_func0_init(struct device *dev)
 {
 	int lightup_ok = 0;
-	u32 reg32;
 
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
 	/* Pre panel init */
 	gma_setup_panel(dev);
 
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+
 	int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
 
 	if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 71ed4c4..183c8f5 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -660,8 +660,6 @@
 
 static void gma_func0_init(struct device *dev)
 {
-	u32 reg32;
-
 	intel_gma_init_igd_opregion();
 
 	/* Unconditionally reset graphics */
@@ -672,9 +670,8 @@
 	while (pci_read_config8(dev, GDRST) & 1)
 		;
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
 		int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
@@ -713,12 +710,10 @@
 
 static void gma_func1_init(struct device *dev)
 {
-	u32 reg32;
 	u8 val;
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	if (get_option(&val, "tft_brightness") == CB_SUCCESS)
 		pci_write_config8(dev, 0xf4, val);
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index 6ba95d3..5ccf8a6 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -135,14 +135,10 @@
 
 static void gma_func0_init(struct device *dev)
 {
-	u32 reg32;
-
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!gtt_res || !gtt_res->base)
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index 7e5b236..2f4b629 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -218,14 +218,10 @@
 
 static void gma_func0_init(struct device *dev)
 {
-	u32 reg32;
-
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
 		/* PCI init, will run VBIOS */
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 6e89b4e..150b61c 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -585,18 +585,14 @@
 
 static void gma_func0_init(struct device *dev)
 {
-	u32 reg32;
-
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+
 	if (!CONFIG(MAINBOARD_USE_LIBGFXINIT))
 		/* PCI Init, will run VBIOS */
 		pci_dev_init(dev);
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 69b6f71..ecbd63e 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -22,14 +22,10 @@
 
 static void gma_func0_init(struct device *dev)
 {
-	u32 reg32;
-
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	/* configure GMBUSFREQ */
 	pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc);
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 0f83937..41167b1 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -496,15 +496,13 @@
 
 	intel_gma_init_igd_opregion();
 
-	/* IGD needs to be Bus Master */
-	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
-
 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!gtt_res || !gtt_res->base)
 		return;
 
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+
 	/* Wait for any configured pre-graphics delay */
 	if (!acpi_is_wakeup_s3()) {
 #if CONFIG(CHROMEOS)
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 6b035bc..ba4bc85 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -45,10 +45,8 @@
 	if (CONFIG(RUN_FSP_GOP))
 		return;
 
-	/* IGD needs to Bus Master */
-	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	if (!CONFIG(NO_GFX_INIT))
+		pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
 	if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 		if (!acpi_is_wakeup_s3() && display_init_required()) {