intel/gma: Only enable bus mastering if we are going to use it
Also fix wrong 32-bit writes.
Change-Id: Ib038f0cd558223536da08ba2264774db11cd8357
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40727
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index b48b3c3..6a51dae 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -144,7 +144,6 @@
static void gma_func0_init(struct device *dev)
{
- u32 reg32;
u8 *mmio;
u8 edid_data_lvds[128];
struct edid edid_lvds;
@@ -152,16 +151,13 @@
intel_gma_init_igd_opregion();
- /* IGD needs to be Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (gtt_res == NULL)
return;
mmio = res2mmio(gtt_res, 0, 0);
+ if (!CONFIG(NO_GFX_INIT))
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
/* PCI Init, will run VBIOS */