arch/x86: remove low coreboot table support
In addition to being consistent with all other architectures,
all chipsets support cbmem so the low coreboot table path is
stale and never taken. Also it's important to note the memory
written in to that low area of memory wasn't automatically
reserved unless that path was taken. To that end remove
low coreboot table support for x86.
Change-Id: Ib96338cf3024e3aa34931c53a7318f40185be34c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 18e8b34..091ceaf 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -447,7 +447,7 @@
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
- unsigned long rom_table_start, unsigned long rom_table_end)
+ unsigned long rom_table_start __unused, unsigned long rom_table_end)
{
struct lb_header *head;
@@ -468,10 +468,6 @@
rom_table_end);
head = lb_table_init(rom_table_end);
- rom_table_end = (unsigned long)head;
- printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
- rom_table_end = ALIGN(rom_table_end, (64 * 1024));
- printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
#if CONFIG_USE_OPTION_TABLE
{
@@ -500,15 +496,6 @@
bootmem_add_range(low_table_start, size, LB_MEM_TABLE);
}
- /* Record the pirq table, acpi tables, and maybe the mptable. However,
- * these only need to be added when the rom_table is sitting below
- * 1MiB. If it isn't that means high tables are being written.
- * The code below handles high tables correctly. */
- if (rom_table_end <= (1 << 20)) {
- uint64_t size = rom_table_end - rom_table_start;
- bootmem_add_range(rom_table_start, size, LB_MEM_TABLE);
- }
-
/* No other memory areas can be added after the memory table has been
* committed as the entries won't show up in the serialize mem table. */
bootmem_write_memory_table(lb_memory(head));