| commit | dcce5a33e95b1fa3c09a0ab0a9e951336cbf096e | [log] [tgz] |
|---|---|---|
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | Tue Aug 08 12:29:23 2023 -0500 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Wed Aug 09 19:08:40 2023 +0000 |
| tree | 78f59c4862137cc3050d7908643fe4d56558e7b3 | |
| parent | 66ff4fb1a565fe5f040e893bd02e52fed3ad2771 [diff] |
mb/google/kahlee: enable uart0 for console in devicetree Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console, so enable uart_0 in the devicetree to make sure that the UART will be marked as enabled in the SSDT that will be generated with the next patch applied. This also matches the other AMD SoC based Chromebooks. Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 632ffa3..92c0d14 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb
@@ -109,4 +109,7 @@ device i2c 10 on end end end + + device ref uart_0 on end # console + end #chip soc/amd/stoneyridge