diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index a2ccbc3..df88ef3 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -43,7 +43,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
-#include <northbridge/intel/common/mrc_cache.h>
+#include <mrc_cache.h>
 #endif
 
 #if !REAL
@@ -91,6 +91,8 @@
 	u8 largest;
 } timing_bounds_t[2][2][2][9];
 
+#define MRC_CACHE_VERSION 1
+
 struct ram_training {
 	/* [TM][CHANNEL][SLOT][RANK][LANE] */
 	u16 lane_timings[4][2][2][2][9];
@@ -1741,17 +1743,18 @@
 	printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8);
 
 	/* Save the MRC S3 restore data to cbmem */
-	store_current_mrc_cache(&train, sizeof(train));
+	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
+			&train, sizeof(train));
 }
 
 #if REAL
 static const struct ram_training *get_cached_training(void)
 {
-	struct mrc_data_container *cont;
-	cont = find_current_mrc_cache();
-	if (!cont)
+	struct region_device rdev;
+	if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
+					&rdev))
 		return 0;
-	return (void *)cont->mrc_data;
+	return (void *)rdev_mmap_full(&rdev);
 }
 #endif